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Freescale Semiconductor Data Sheet: Product Preview
Document Number: MPC8535EEC Rev. 2, 09/2009
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications
* High-performance, 32-bit e500 core, scaling up to 1.25 GHz, that implements the Power ArchitectureTM technology - 36-bit physical addressing - Double-precision embedded floating point APU using 64-bit operands - Embedded vector and scalar single-precision floating-point APUs using 32- or 64-bit operands - Memory management unit (MMU) * Integrated L1/L2 cache - L1 cache--32-Kbyte data and 32-Kbyte instruction - L2 cache--512-Kbyte (8-way set associative) * DDR2/DDR3 SDRAM memory controller with full ECC support - One 64-bit/32-bit data bus - Up to 250-MHz clock (500-MHz data rate) - Supporting up to 16 Gbytes of main memory - Using ECC, detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble - Invoke a level of system power management by asserting MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode - Both hardware and software options to support battery-backed main memory * Integrated security engine (SEC) optimized to process all the algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, IEEE Std 802.16eTM, and 3GPP. - XOR engine for parity checking in RAID storage applications * Enhanced Serial peripheral interfaces (eSPI) - Support boot capability from eSPI * Two enhanced three-speed Ethernet controllers (eTSECs) with SGMII support - Three-speed support (10/100/1000 Mbps) - Two IEEE Std 802.3TM, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and IEEE Std 1588TM-compatible controllers
FC-PBGA-783 29 mm x 29 mm
*
* * * *
* * * *
* * *
- Support for various Ethernet physical interfaces: GMII, TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII - Support TCP/IP acceleration and QOS features - MAC address recognition and RMON statistics support - Support ARP parsing and generating wake-up events based on the parsing results while in deep sleep mode - Support accepting and storing packets while in deep sleep mode High-speed interfaces (multiplexed) supporting: - Two PCI Express interfaces - PCI Express 1.0a compatible - One x4/x2/x1 PCI Express interface - Two x2/x1 ports - One SGMII interface - One Serial ATA (SATA) Controller supports SATA I and SATA II data rates PCI 2.2 compatible PCI controller Two universal serial bus (USB) dual-role controllers comply with USB specification revision 2.0 133-MHz, 32-bit, enhanced local bus (eLBC) with memory controller Enhanced secured digital host controller (eSDHC) used for SD/MMC card interface - Support boot capability from eSDHC Integrated four-channel DMA controller Dual I2C and dual universal asynchronous receiver/transmitter (DUART) support Programmable interrupt controller (PIC) Power management, low standby power - Support Doze, Nap, Sleep, Jog, and Deep Sleep mode - PMC wake on: LAN activity, USB connection or remote wakeup, GPIO, internal timer, or external interrupt event System performance monitor IEEE Std 1149.1TM-compatible, JTAG boundary scan 783-pin FC-PBGA package, 29 mm x 29 mm
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice.
(c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1 2 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3 1.1 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21 2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .31 2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.10 Ethernet Management Interface Electrical Characteristics 60 2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.12 enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .65 2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .74 2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .76 2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 2.17 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .90 3 2.21 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.23 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 113 3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.2 Power Supply Design and Sequencing . . . . . . . . . . . 113 3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 114 3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 114 3.5 SerDes Block Power Supply Decoupling Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 115 3.7 Pull-Up and Pull-Down Resistor Requirements . . . . . 115 3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 115 3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 116 3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 117 3.11 Guidelines for High-Speed Interface Termination . . . 119 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.1 Part Numbers Fully Addressed by This Document . . 121 4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.1 Package Parameters for the MPC8535E FC-PBGA . 122 5.2 Mechanical Dimensions of the MPC8535E FC-PBGA123 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 124
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MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor
Figure 1 shows the major functional units within the MPC8535E.
e500 Core
32-Kbyte D-Cache 32-Kbyte I-Cache 512-Kbyte L2 Cache Power Management
MPC8535E
Performance Monitor Timers
Enhanced Local Bus
SEC
OpenPIC
Coherency Module
eSPI DUART 2x I2C
64-bit Async DDR2/DDR3 Queue SDRAM Controller with ECC
SD MMC
USB Host/ Device ULPI
USB Host/ Device ULPI
Gigabit Ethernet w/ IEEE 1588
Gigabit Ethernet w/ IEEE 1588 SGMII SerDes
PCI 32 SATA PCI-e
DMA
PCI-e
4 Lane SerDes
Figure 1. MPC8535E Block Diagram
1
Pin Assignments and Reset States
NOTE The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails for the eTSEC blocks and to ease the port of existing PowerQUICC III software NOTE The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Please refer to Table 1 for more details.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 3
Pin Map
1.1
Pin Map
See Table 1 for the MPC8535E pinout, which is a subset of the MPC8536E. Figure 2 provides a bottom view of the pin map of the MPC8536E.
A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MDQ [44]
B
GVDD MDQ [40] MDQ [45]
C
MDQS [5] MDM [5] MDQ [41] MCS [2] MRAS
D
MDQ [32] MDQS [5] MCS [0] GVDD
E
MDQ [46] GVDD
F
MDQ [47] MDQ [42] MDQ [33]
G
MDQ [34] MDQ [43] GVDD MDM [4] MDQ [37] MCS [3] GVDD MA [1]
H
GND MDQ [35] MDQ [38]
J
MDQ [56] MDQ [60] MDQ [52] MDQ [39] MDQS [4] MCK [2]
K
MDQ [57] MDQ [61] GVDD MDQ [53] MDQS [4] MCK [2] GND
L
GND MDM [7] MDM [6] MDQ [49] MDQ [48]
M
GVDD MDQS [7] MDQS [6] MDQS [6]
N
MDQS [7]
P
MDQ [58] MDM [62] MDQ [51] MDQ [55]
R
MDQ [59] MDQ [63] GVDD Rvsd
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
USB1_ DIR USB1_ PWRFAULT
AVDD_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_ USB1_D USB1_D USB1_ RXD SRDS2 RX_CLK RXD TX_EN RX_DV CLK STP [0] [2] [5] [7] [3] [1] AGND_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D USB1_ RXD SRDS2 RXD NXT RX_DV GTX_CLK RXD [1] [3] [4] [6] [1] [0] [3] SD2_ PLL_ TPA TSEC3_ RX_ER TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ USB1_ USB2_D USB2_D PCTL0/ RXD RXD TXD RXD RX_CLK RXD [0] [1] GPIO[6] [2] [0] [3] [2] [7] GND TVDD TSEC1_ TXD [1] GND LVDD USB1_ TSEC1_ PCTL1/ TX_CLK GPIO[7] GND OVDD GND OVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND MDQ [50] MDQ [54] GVDD
GND MBA [0] MA [10] MAPAR_ OUT GND MCK [3] MCK [0] MA [3] MA [6] MA [11] MAPAR_ ERR GND MDQ [26] MDQ [30] MDQS [3] MDQ [25] MDQ [29] MDQ [11] MDQ [15] MDQS [1] MDQ [9] MDQ [8] MDQ [12] MDQ [0]
GND MDQ [36] MODT [0] MODT [2]
USB3_D USB3_D [1] [0]
MWE MBA [1]
GND
GND
USB2_D USB2_D USB3_D USB3_D [3] [2] [2] [3]
GND
GVDD MODT [3] MA [13]
GVDD MCS [1] MODT [1] MCK [5]
GND
GND
Rvsd
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD GTX_CLK TX_EN TXD TXD TXD TX_ER [1] [2] [4] [6]
USB2_ USB2_D USB2_D USB3_D USB3_ [4] CLK [4] [5] CLK
NC MA [0] MCK [3] MCK [0]
GND
GVDD
SD2_ SD2_ IMP_CAL REF_ _TX CLK SD2_ PLL_ TPD Rsvd SD2_ REF_ CLK S2GND
DMA_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D SD2_RX DACK[0]/ USB2_D OVDD USB3_D USB3_D S2VDD S2GND TXD RXD RXD TXD RXD CLK125 COL [5] [6] [7] [0] [6] GPIO[10] [0] [5] [4] [0] [4] SD2_ TSEC3_ S2VDD SD2_RX IMP_CAL TXD [0] _RX [2] SD2_RX S2GND [1] NC TVDD GND TSEC_ 1588_TRIG _IN[1] GND LVDD TSEC1_ USB2_ RXD NXT [6] USB2_ STP GND USB2_ DIR USB3_ USB3_D NXT [7] USB3_ DIR USB2_ PCTL0/ GPIO[8] USB3_ STP Rsvd
GVDD MA [2] GVDD MA [5] MECC [3]
NC
MCAS
NC MCK [5]
SEE DETAIL A
GND MA [4] GVDD MA [8] MA [14] GVDD GND MA [7] MA [15] MECC [2] GND GVDD MCKE [2] GVDD MECC [0] MCKE [3] MCKE [0] MCK [1] GVDD MCK [4] NC NC
TSEC3_ TSEC3_ TSEC3_ TSEC_ TSEC1_ TSEC1_ TSEC1_ USB2_ PWRTXD TXD TXD 1588_TRIG TXD RXD TXD FAULT [5] [5] [7] _IN[0] [3] [5] [6]
SEE DETAIL B
USB2_ PCTL1/ GPIO[9]
GND
NC MA [12] MECC [7] MDQS [8] MECC [1] GVDD MDQ [23]
GVDD MCK [1]
MCKE [1]
GVDD MA [9] MBA [2] MDQ [27] MDQ [31] MDQS [3] MDM [3] MDQ [24] MDQ [28] MDQ [10] MDQ [14] MDQS [1] MDM [1] MDQ [13] MDQ [5] MDQ [1] LDP [2]
GND
TSEC3_ TSEC3_ TSEC3_ TSEC_ TSEC1_ TSEC1_ GND NC Rsvd 1588_ TXD COL TX_ER RX_ER CRS CLK [4] SDHC_ DMA_ TSEC_ TSEC_ EC_ TSEC3_ TSEC3_ 1588_CLK 1588_TRIG DAT[7]/SPI DREQ[0]/ NC NC NC NC X2GND MDC CRS TX_CLK _OUT _OUT[1] _CS[3] GPIO[14] TSEC_ TSEC_ TSEC_ DMA_ DMA_ EC_ SD2_TX SD2_TX 1588_PULSE 1588_TRIG1588_PULSE MSRCID DDONE[0]/ DDONE[1]/ X2GND X2VDD X2VDD MDIO GPIO[12] GPIO[13] [4] [1] [0] _OUT2 _OUT[0] _OUT1 SD2_RX S2GND S2VDD [1] TSEC3_ TSEC3_ MSRCID MSRCID UART_ SD2_TX X2GND SD2_TX X2VDD X2GND TXD CTS RXD [2] [0] [1] [0] [7] [7] [1] GND VDD_ CORE GND VDD_ CORE GND LCS7/ DMA_ DDONE2 LA [27] VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ PLAT GND VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ PLAT XVDD GND VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ PLAT XVDD TSEC3_ MDVAL MSRCID RXD [1] [6] VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND SENSEVDD_ CORE SENSEVSS VDD_ PLAT MSRCID [3] CLK_ OUT PCI1_ REQ [1] SENSEVDD_ PLAT GND UART_ SOUT [1] TEST_ SEL GND UART_ RTS [0]
SDHC_ SPI_ SPI_ DAT[4]/SPI CLK MOSI _CS[0] SDHC_ SPI_ GND DAT[6]/SPI MISO _CS[2] DMA_ DACK[1]/ GPIO[11] UART_ CTS [0]
SDHC_ DAT[5]/SPI OVDD _CS[1] GND UART_ SIN [0] DMA_ DREQ[1]/ GPIO[15]
UART_ SDHC_ SDHC_ SOUT WP/GPIO CMD [0] [5] SDHC_ SDHC_ OVDD CD/GPIO DAT [3] [4] UART_ SIN [1] PCI1_ REQ [2] PCI1_ GNT [2] RTC IRQ [5] IRQ [1] PCI1_ AD [18] IRQ [3] SDHC_ SDHC_ DAT DAT [1] [0] SDHC_ SDHC_ DAT CLK [2] IIC2_ SDA HRESET_ REQ SYSCLK IIC2_ SCL
GND MECC [6]
GND
NC MDM [8] MECC [5] GVDD
GND MCK [4]
GVDD VDD_ CORE GVDD MDIC [1] LA [28] LA [29] LCS [0]
MDQS [8]
GND MECC [4]
GVDD
GVDD
GVDD MDIC [0] LCS5/ DMA_ DREQ2 LA [30] LGPL3/ LFWP LCS [2] LCS [3] LWE[3]/ LBS[3] LWE[1]/ LBS[1]
GND
MCP
UART_ GND RTS [1] IRQ[10]/ IRQ[9]/ DMA_ OVDD DDRCLK DMA_ DACK[2] DREQ[2] IRQ[11]/ PCI1_GNT OVDD UDE [4]/GPIO DMA_ DDONE[2] [3] PCI1_ AD [31] OVDD PCI1_ AD [27] PCI1_ AD [22] PCI1_ AD [21] PCI1_ IRDY PCI1_ AD [28] PCI1_ AD [26] IRQ_ OUT OVDD PCI1_ AD [19] PCI1_ AD [16] GND PCI1_REQ [4]/GPIO [1] PCI1_ IDSEL PCI1_ AD [23] PCI1_ AD [20] PCI1_ AD [17] PCI1_ FRAME GND
GND MDQ [19] GVDD MDQS [2]
GND MDQ [18] MDQS [2] GVDD MDQ [16]
GND
GND LCS6/ DMA_ DACK2 GND
PCI1_REQ PCI1_GNT [3]/GPIO [3]/GPIO [0] [2] PCI1_ GNT [1] PCI1_ AD [30] PCI1_ REQ [0] PCI1_ AD [29] PCI1_ AD [25] GND L2_ TSTCLK
GND
LCS [4] LA [31]
OVDD PCI1_ AD [24] PCI1_ C_BE [3] GND PCI1_ C_BE [2] PCI1_ STOP PCI1_ C_BE [1] GND PCI1_ AD [7] OVDD
AVDD_ HRESET CORE IRQ [4] CKSTP_ OUT
GND MDM [2] MDQ [17] GVDD MDQ [3] MDQ [6]
MDQ [22] MDQ [21] MDQ [20] BVDD
GND
BVDD
NC
LCS [1]
LGPL2/ LOE/ LFRE
BVDD
LGPL5
PCI1_ OVDD GND GNT [0] TRIG_ IRQ GND OUT/READY TRIG_IN [7] /QUIESCE XGND SD1_TX [6] XVDD
CKSTP_ AVDD_ PLAT IN AVDD_ SRESET DDR
GND
GND MDQ [7] GVDD LAD [27] LAD [24] LDP [3] LAD [22] LAD [21] LAD [20]
LGPL4/ LGTA/ LGPL0/ LGPL1/ LUPWAIT/ LFCLE LFALE LPBSE/ XGND LFRB
SD1_TX [1] SD1_TX [1]
SD1_TX [3]
SD1_TX [4] SD1_TX [4] XGND
AVDD_ OVDD ASLEEP PCI1 PCI1_ TRDY PCI1_ SERR PCI1_ AD [15] OVDD PCI1_ AD [4] PCI1_ AD [2] IIC1_ SCL IRQ [0] TRST IIC1_ SDA PCI1_ AD [11] PCI1_ AD [12] PCI1_ C_BE [0] PCI1_ CLK TMS
GVDD MDQ [2] MDQS [0] GVDD MDM [0] LAD [25]
GND LAD [29]
LAD [31] LAD [30] LAD [28] LAD [26]
BVDD
LWE0/ LBS0/ LFWE
GND LAD [0] LAD [3] LAD [4] LAD [7] LDP [0] LAD [11] LAD [10]
LAD [1] LAD [2]
XVDD
XGND
SEE DETAIL C
BVDD LAD [23] LAD [19] LAD [18] LWE[2]/ LBS[2] LCLK [0] LCLK [2] BVDD LCLK [1]
SD1_TX XGND [3] XVDD Rsvd
XVDD SD1_TX [5] SD1_TX [5] SGND
L1_ SD1_TX XGND TSTCLK [6] XVDD SD1_TX [7] SD1_TX [7] SVDD SD1_RX [4] IRQ [6]
SD1_TX XGND [0] SD1_TX [0] XGND XVDD
SD1_TX [2] SD1_TX [2] SGND
SEE DETAIL D
IRQ [8] PCI1_ PAR XVDD IRQ [2] PCI1_ AD [13] PCI1_ AD [5]
PCI1_ PCI1_ PERR DEVSEL
OVDD PCI1_ AD [14] PCI1_ AD [9] PCI1_ AD [1] GND
GND
BVDD LAD [5] LAD [6]
XGND
Rsvd
XVDD
XGND
GND PCI1_ AD [10] PCI1_ AD [8] PCI1_ AD [3] PCI1_ AD [6] TCK
MDQS [0] MDQ [4]
NC
SVDD
SVDD
SGND
SVDD
SGND
SGND
GND
LBCTL
NC
SVDD
SD1_RX [1] SD1_RX [1] SGND
SGND SD1_RX [3] SVDD SD1_RX [3] SD1_RX SV DD [2] SD1_RX SGND [2]
SVDD
NC SD1_ PLL_ TPA AGND_ SRDS SD1_ PLL_ TPD
SGND
SVDD
SD1_RX LSSD_ [6] MODE
GND
LAD [16] LAD [15] LDP [1]
BVDD LAD [14] LAD [13]
LALE
GND LAD [9] LAD [8]
SD1_ IMP_CAL SGND _RX SVDD SD1_RX [0] SD1_RX [0]
SGND SD1_ REF_ CLK SD1_ REF_ CLK
SVDD SD1_RX [4] NC AVDD_ SRDS SVDD
SGND SD1_RX [5] SD1_RX [5]
SD1_RX POWER_ PCI1_ AD OK [6] [0] SGND SD1_RX [7]
GND
GND
LSYNC_ IN
GND LAD [17]
GND LAD [12]
SVDD POWER_ OVDD EN SD1_ SGND IMP_CAL _TX TDO
MVREF
GND
AVDD_ LSYNC_ OUT LBIU
SGND
SVDD
SGND
SVDD SD1_RX [7]
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
Figure 2. MPC8535E Pin Map Bottom View
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 4 Freescale Semiconductor
Pin Map
A 1
MDQ [44]
B
GVDD MDQ [40] MDQ [45]
C
MDQS [5] MDM [5] MDQ [41] MCS [2]
D
MDQ [32] MDQS [5] MCS [0]
E
MDQ [46]
F
MDQ [47] MDQ [42] MDQ [33]
G
MDQ [34] MDQ [43]
H
GND
J
MDQ [56] MDQ [60] MDQ [52] MDQ [39] MDQS [4] MCK [2]
K
MDQ [57] MDQ [61]
L
GND
M
GVDD
N
MDQS [7]
P
MDQ [58] MDM [62] MDQ [51] MDQ [55]
2
GVDD
MDQ [35] MDQ [38]
MDM [7] MDM [6] MDQ [49] MDQ [48] SD2_ IMP_CAL _TX SD2_ PLL_ TPD Rsvd
MDQS [7] MDQS [6] MDQS [6]
GND
3
GND
GND
GVDD
GVDD
MDQ [50] MDQ [54]
4
MBA [0] MA [10] MAPAR_ OUT
MWE
GVDD
MDQ [36] MODT [0] MODT [2]
GND
MDM [4] MDQ [37] MCS [3] GVDD
GND
MDQ [53] MDQS [4] MCK [2]
5
MBA [1]
MRAS
GND
GVDD MODT [3] MA [13]
GVDD
GND SD2_ REF_ CLK SD2_ REF_ CLK S2GND
GVDD
GND
6
NC
GND
GVDD
MCS [1] MODT [1] MCK [5] MCKE [3] MCKE [0] MCK [1]
S2GND
SD2_RX [0] SD2_RX [0] S2GND
7
GND
MA [0] MCK [3] MCK [0]
GVDD
NC
MCAS
NC
GND
S2VDD SD2_RX [1] SD2_RX [1] NC
8
MCK [3] MCK [0] MA [3] MA [6] MA [11] MAPAR_ ERR GND
MA [2]
GND
GVDD
GND
MA [1]
MCK [5]
GND
9
GVDD
MA [4]
MA [8] MA [14]
MA [7] MA [15] MECC [2]
GVDD
NC
NC
Rsvd
S2VDD
S2GND
10
GND
MA [5] MECC [3]
NC
MCKE [2]
GVDD
MCKE [1]
NC
X2GND
NC
11
GVDD
MA [12] MECC [7] MDQS [8] MECC [1]
GVDD
GVDD
MCK [1]
GND
X2VDD
SD2_TX [1] SD2_TX [1] VDD_ CORE
X2GND
SD2_TX [0] SD2_TX [0] VDD_ CORE
12
MA [9] MBA [2] MDQ [27]
GND
GND
NC
MECC [0]
GVDD
GND
GVDD
X2GND
X2VDD
13
MECC [6]
MDQS [8]
MDM [8] MECC [5]
GND
MCK [4]
MCK [4]
VDD_ CORE GVDD
GND
GND
14
GVDD
GVDD
MECC [4]
GVDD
GND
VDD_ CORE
GND
VDD_ CORE
GND
DETAIL A Figure 3. MPC8535E Pin Map Detail A
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 5
Pin Map
R
MDQ [59] MDQ [63]
T
AVDD_ SRDS2 AGND_ SRDS2 SD2_ PLL_ TPA TSEC3_ RX_ER
U
V
W
Y
AA
AB
AC
AD
USB1_ CLK
AE
AF
AG
USB1_ STP OVDD
AH
USB1_ DIR USB1_ PWRFAULT
TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D RXD RX_CLK RXD TX_EN RX_DV [0] [2] [3] [1]
USB1_D USB1_D [7] [5] USB1_ NXT
1
TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D RXD RXD RX_DV GTX_CLK RXD [6] [1] [3] [4] [1] [0] [3] TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ RXD RXD TXD RXD RXD RX_CLK [2] [0] [3] [2] [7] GND TVDD TSEC1_ TXD [1] GND LVDD TSEC1_ TX_CLK USB1_ PCTL0/ GPIO[6] USB1_ PCTL1/ GPIO[7] GND USB2_D USB2_D [0] [1] OVDD
2
GVDD
GND
USB3_D USB3_D [1] [0]
3
Rvsd
USB2_D USB2_D USB3_D USB3_D [3] [2] [2] [3] USB2_D USB2_D USB3_D [4] [4] [5] USB2_D [7] GND SDHC_ DAT[4]/SPI _CS[0] GND DMA_ DACK[1]/ GPIO[11] UART_ CTS [0] GND IRQ[9]/ DMA_ DREQ[2] OVDD OVDD USB2_ DIR SPI_ MOSI USB3_ CLK
4
Rvsd
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD TXD GTX_CLK TX_EN TX_ER [1] [2] [4] [6]
USB2_ CLK
5
S2VDD
DMA_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D DACK[0]/ TXD RXD RXD TXD RXD COL [6] CLK125 GPIO[10] [0] [5] [4] [0] [4] TVDD GND TSEC_ 1588_TRIG _IN[1] GND LVDD TSEC1_ RXD [6] USB2_ NXT USB2_ PWRFAULT USB2_ STP SPI_ CLK SPI_ MISO
USB3_D USB3_D [5] [6] USB3_ NXT USB3_ DIR USB3_D [7] USB3_ STP Rsvd
6
SD2_ TSEC3_ IMP_CAL TXD _RX [2] NC
7
TSEC_ TSEC1_ TSEC1_ TSEC1_ TSEC3_ TSEC3_ TSEC3_ 1588_TRIG TXD RXD TXD TXD TXD TXD _IN[0] [5] [5] [7] [3] [5] [6] TSEC3_ TSEC3_ TSEC3_ TXD COL TX_ER [4]
8
NC
NC
USB2_ TSEC_ TSEC1_ TSEC1_ PCTL1/ GND 1588_ RX_ER CRS GPIO[9] CLK TSEC_ SDHC_ SDHC_ TSEC_ DMA_ TSEC3_ TSEC3_ 1588_CLK 1588_TRIG EC_ DAT[7]/SPI DREQ[0]/ DAT[5]/SPI MDC CRS TX_CLK _OUT _OUT[1] _CS[3] GPIO[14] _CS[1] EC_ MDIO UART_ CTS [1] GND DMA_ DMA_ DDONE[0]/ DDONE[1]/ GPIO[12] GPIO[13] UART_ SOUT [1] TEST_ SEL GND UART_ RTS [0] OVDD GND UART_ SIN [0] DDRCLK
SDHC_ USB2_ DAT[6]/SPI PCTL0/ GPIO[8] _CS[2] UART_ SOUT [0] OVDD UART_ SIN [1] PCI1_ REQ [2] PCI1_ GNT [2] SDHC_ WP/GPIO [5] SDHC_ DAT [3] SDHC_ DAT [0] SDHC_ CLK IIC2_ SDA
9
OVDD DMA_ DREQ[1]/ GPIO[15] UART_ RTS [1] IRQ[10]/ DMA_ DACK[2]
SDHC_ CMD SDHC_ CD/GPIO [4] SDHC_ DAT [1] SDHC_ DAT [2] SYSCLK
10
TSEC_ TSEC_ TSEC_ X2VDD 1588_PULSE 1588_TRIG 1588_PULSE MSRCID [4] _OUT[0] _OUT2 _OUT1 X2GND TSEC3_ TSEC3_ MSRCID MSRCID TXD RXD [0] [2] [7] [7] VDD_ CORE TSEC3_ RXD [6] VDD_ CORE MDVAL MSRCID [1] MSRCID [3]
11
12
GND
13
VDD_ CORE
GND
GND
MCP
UDE
PCI1_GNT IRQ[11]/ DMA_ [4]/GPIO DDONE[2] [3]
14
DETAIL B Figure 4. MPC8535E Pin Map Detail B
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 6 Freescale Semiconductor
Pin Map
DETAIL C
15
MDQ [26] MDQ [30] MDQS [3] MDQ [25] MDQ [29] MDQ [11] MDQ [15] MDQS [1] MDQ [9] MDQ [8] MDQ [12] MDQ [0] MDQ [31] MDQS [3] MDM [3] MDQ [24] MDQ [28] MDQ [10] MDQ [14] MDQS [1] MDM [1] MDQ [13] MDQ [5] MDQ [1] LDP [2] GND GVDD GND GVDD GND MDIC [0] LCS5/ DMA_ DREQ2 LA [30] LGPL3/ LFWP LCS [2] LCS [3] LWE[3]/ LBS[3] LWE[1]/ LBS[1] LWE[2]/ LBS[2] LCLK [0] LCLK [2] GND LCS6/ DMA_ DACK2 GND MDIC [1] LA [28] LA [29] LCS [0] GND VDD_ CORE GND VDD_ CORE
16
MDQ [19]
MDQ [23]
MDQ [18] MDQS [2]
GND
LCS [4] LA [31]
VDD_ CORE
GND
VDD_ CORE
GND
17
GVDD
GND
MDQ [22] MDQ [21] MDQ [20]
GND LCS7/ DMA_ DDONE2 LA [27]
VDD_ PLAT
GND
VDD_ PLAT
18
MDQS [2]
MDM [2] MDQ [17]
GVDD MDQ [16]
GND
BVDD
GND
VDD_ PLAT
GND
19
NC
LCS [1] LGPL2/ LOE/ LFRE LAD [31] LAD [30] LAD [28] LAD [26]
BVDD
LGPL5
VDD_ PLAT
GND
VDD_ PLAT XVDD
20
GND
GVDD
GND
BVDD
LGPL0/ LFCLE BVDD LWE0/ LBS0/ LFWE BVDD
LGPL4/ LGTA/ LGPL1/ LUPWAIT/ XGND LFALE LPBSE/ LFRB GND LAD [1] LAD [2] XVDD
SD1_TX [1] SD1_TX [1] XGND
21
GVDD
MDQ [3] MDQ [6]
MDQ [7]
GND
XGND
22
MDQ [2] MDQS [0]
GVDD
LAD [29]
LAD [0] LAD [3] LAD [4] LAD [7] LDP [0] LAD [11] LAD [10]
SD1_TX [0] SD1_TX [0] XGND
SD1_TX [2] SD1_TX [2] SGND
23
GND
LAD [27] LAD [24] LDP [3] LAD [22] LAD [21] LAD [20]
BVDD
BVDD
XVDD
24
GVDD
MDQS [0] MDQ [4]
LAD [23] LAD [19] LAD [18]
LCLK [1]
LAD [5] LAD [6]
NC
25
MDM [0] LAD [25]
GND
LBCTL
NC SD1_ IMP_CAL _RX SVDD
SVDD
SD1_RX [1] SD1_RX [1] SGND
26
GND
LAD [16] LAD [15] LDP [1]
BVDD LAD [14] LAD [13]
LALE
GND
SGND
27
GND
GND
LSYNC_ IN LSYNC_ OUT
GND
GND
LAD [9] LAD [8]
SD1_RX [0] SD1_RX [0]
28
MVREF
GND
AVDD_ LBIU
LAD [17]
LAD [12]
SGND
SVDD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 5. MPC8535E Pin Map Detail C
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 7
Pin Map
DETAIL D
GND VDD_ CORE GND SENSEVDD_ CORE SENSEVSS VDD_ PLAT CLK_ OUT PCI1_ REQ [1] SENSEVDD_ PLAT PCI1_ GNT [0] PCI1_REQ PCI1_GNT [3]/GPIO [3]/GPIO [0] [2] PCI1_ GNT [1] PCI1_ AD [30] OVDD IRQ [7] PCI1_ REQ [0] PCI1_ AD [29] PCI1_ AD [25] GND L2_ TSTCLK L1_ TSTCLK IRQ [6] PCI1_ AD [31] OVDD PCI1_ AD [27] PCI1_ AD [22] PCI1_ AD [21] PCI1_ IRDY PCI1_ PERR IRQ [8] IRQ [2] PCI1_ AD [28] PCI1_ AD [26] IRQ_ OUT OVDD PCI1_ AD [19] PCI1_ AD [16] PCI1_ DEVSEL PCI1_ PAR PCI1_ AD [13] PCI1_ AD [5] LSSD_ MODE GND PCI1_REQ [4]/GPIO [1] PCI1_ IDSEL PCI1_ AD [23] PCI1_ AD [20] PCI1_ AD [17] PCI1_ FRAME RTC HRESET_ REQ HRESET IIC2_ SCL AVDD_ CORE CKSTP_ OUT AVDD_ PLAT AVDD_ DDR AVDD_ PCI1
15
VDD_ CORE
GND
VDD_ CORE
OVDD PCI1_ AD [24] PCI1_ C_BE [3] GND PCI1_ C_BE [2] PCI1_ STOP PCI1_ C_BE [1] GND PCI1_ AD [7] OVDD PCI1_ AD [0] SVDD
IRQ [5] IRQ [1] PCI1_ AD [18] IRQ [3]
16
GND
VDD_ PLAT
GND
IRQ [4] CKSTP_ IN SRESET
17
VDD_ PLAT
GND
VDD_ PLAT
GND
18
GND
VDD_ PLAT XVDD
GND
TRIG_ OUT/READY TRIG_IN /QUIESCE XGND SD1_TX [6] SD1_TX [6] XVDD
19
SD1_TX [3] SD1_TX [3] XVDD
SD1_TX [4] SD1_TX [4]
XVDD
OVDD PCI1_ TRDY PCI1_ SERR PCI1_ AD [15] OVDD PCI1_ AD [4] PCI1_ AD [2] OVDD
ASLEEP
20
XGND
XVDD SD1_TX [5] SD1_TX [5] SGND
XGND
GND
IIC1_ SCL IRQ [0]
TRST
21
Rsvd
XGND
SD1_TX [7] SD1_TX [7] SVDD
OVDD PCI1_ AD [14] PCI1_ AD [9] PCI1_ AD [1] GND
IIC1_ SDA PCI1_ AD [11] PCI1_ AD [12] PCI1_ C_BE [0] PCI1_ CLK
22
XGND
Rsvd
XVDD
XGND
XVDD
GND PCI1_ AD [10] PCI1_ AD [8] PCI1_ AD [3] PCI1_ AD [6] TCK
23
SVDD
SVDD
SGND
SVDD
SGND
SGND
24
SGND
SD1_RX [3] SD1_RX [3] SVDD
SVDD
NC SD1_ PLL_ TPA AGND_ SRDS SD1_ PLL_ TPD
SGND
SD1_RX [4] SD1_RX [4] SVDD
SVDD
SD1_RX [6]
25
SVDD SD1_RX [2] SD1_RX [2]
SGND SD1_ REF_ CLK SD1_ REF_ CLK
SVDD
SGND
SD1_RX POWER_ OK [6] SGND SD1_RX [7] SD1_RX [7]
26
NC AVDD_ SRDS
SD1_RX [5] SD1_RX [5]
POWER_ EN SD1_ IMP_CAL _TX
TMS
27
SGND
SGND
SVDD
SGND
TDO
TDI
28
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
Figure 6. MPC8535E Pin Map Detail D
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 8 Freescale Semiconductor
Pin Map
Table 1 provides the pin-out listing for the MPC8535E 783 FC-PBGA package.
3
Table 1. MPC8535E Pinout Listing
Signal Signal Name Package Pin Number PCI Pin Type Power Supply Notes
PCI1_AD[31:0]
Muxed Address / data
AB15,Y17,AA17,AC15, AB17,AC16,AA18, AD17,AE17,AB18, AB19,AE18,AC19, AF18,AE19,AC20, AF23,AE23,AC23, AH24,AH23,AG24, AE24,AG25,AD24, AG27,AC24,AF25, AG26,AF26,AE25, AD26 AD18, AD20,AD22, AH25 AC22 AE20 AF21 AB20 AD21 AC21 AE16 AB21 AF22 AE15,Y15 AF13,W16 AA16 AC14, AA15 AF14,Y16 W18 AH26
I/O
OVDD
--
PCI1_C_BE[3:0] PCI1_PAR PCI1_FRAME PCI1_TRDY PCI1_IRDY PCI1_STOP PCI1_DEVSEL PCI1_IDSEL PCI1_PERR PCI1_SERR PCI1_REQ[4:3]/GPIO[1:0] PCI1_REQ[2:1] PCI1_REQ[0] PCI1_GNT[4:3]/GPIO[3:2] PCI1_GNT[2:1] PCI1_GNT[0] PCI1_CLK
Command/Byte Enable Parity Frame Target Ready Initiator Ready Stop Device Select Init Device Select Parity Error System Error Request Request Request Grant Grant Grant PCI Clock
I/O I/O I/O I/O I/O I/O I/O I I/O I/O I I I/O O O I/O I
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
29 29 2,29 2,29 2,29 2,29 2,29 29 2,29 2,4,29 -- 29 29
5,9,25,29 29 29
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 9
Pin Map
Table 1. MPC8535E Pinout Listing
Signal Signal Name Package Pin Number Pin Type Power Supply Notes
DDR SDRAM Memory Interface MDQ[0:63] Data A26,B26,C22,D21,D25, B25,D22,E21,A24,A23, B20,A20,A25,B24,B21, A21,E19,D19,E16,C16, F19,F18,F17,D16,B18, A18,A15,B14,B19,A19, A16,B15,D1,F3,G1,H2, E4,G5,H3,J4,B2,C3,F2, G2,A2,B3,E1,F1,L5,L4, N3,P3,J3,K4,N4,P4,J1, K1,P1,R1,J2,K2,P2,R2 G12,D14,F11,C11, G14,F14,C13,D12 A13 A6 C25,B23,D18,B17,G4, C2,L3,L2,F13 D24,B22,C18,A17,J5, C1,M4,M2,E13 C23,A22,E17,B16,K5, D2,M3,N1,D13 B7,G8,C8,A10,D9,C10, A11,F9,E9,B12,A5, A12,D11,F7,E10,F10 A4,B5,B13 B4 C5 E7 D3,H6,C4,G6 H10,K10,G10,H9 A9,J11,J6,A8,J13,H8 B9,H11,K6,B8,H13,J8 E5,H7,E6,F6 H15,K15 Local Bus Controller Interface I/O GVDD --
MECC[0:7] MAPAR_ERR MAPAR_OUT MDM[0:8] MDQS[0:8] MDQS[0:8] MA[0:15]
Error Correcting Code Address Parity Error Address Parity Out Data Mask Data Strobe Data Strobe Address
I/O I O O I/O I/O O
GVDD GVDD GVDD GVDD GVDD GVDD GVDD
-- -- -- -- -- -- --
MBA[0:2] MWE MRAS MCAS MCS[0:3] MCKE[0:3] MCK[0:5] MCK[0:5] MODT[0:3] MDIC[0:1]
Bank Select Write Enable Row Address Strobe Column Address Strobe Chip Select Clock Enable Differential Clock 3 Pairs / DIMM Differential Clock 3 Pairs / DIMM On Die Termination Calibration
O O O O O O O O O I/O
GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD
-- -- -- -- -- 11 -- -- -- 26
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 10 Freescale Semiconductor
Pin Map
Table 1. MPC8535E Pinout Listing
Signal LAD[0:31] Signal Name Muxed data / address Package Pin Number K22,L21,L22,K23,K24, L24,L25,K25,L28,L27, K28,K27,J28,H28,H27, G27,G26,F28,F26,F25, E28,E27,E26,F24,E24, C26,G24,E23,G23,F22, G22,G21 K26,G28,B27,E25 L19 K16,K17,H17,G17 K18,G19,H19,H20,G16 Pin Type I/O Power Supply BVDD Notes 5,9,29
LDP[0:3] LA[27] LA[28:31] LCS[0:4] LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LFWE LWE[1:3]/LBS[1:3] LBCTL LALE LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE/LFRE
Data parity Burst address Port address Chip selects
I/O O O O I/O O O O O O O O O O
BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD
29 5,9,29 5,7,9,29 29 1,29 1,29 1,29 5,9,29 5,9,29 5,8,9,29 5,8,9,29 5,9,29 5,9,29 5,8,9,29
Chips selects / DMA Request H16 Chips selects / DMA Ack Chips selects / DMA Done Write enable / Byte select Write enable / Byte select Buffer control Address latch enable J16 L18 J22 H22,H23,H21 J25 J26
UPM general purpose line 0 / J20 FLash command latch enable UPM general purpose line 1 / K20 Flash address latch enable UPM general purpose line 2 / G20 Output enable/Flash read enable UPM general purpose line 3 / H18 Flash write protect UPM general purpose line 4 / L20 Target Ack/Wait/SDRAM parity byte select/Flash Ready-busy UPM general purpose line 5 / K19 Amux Local bus clock Synchronization Local bus DLL H24,J24,H25 D27 D28 DMA
LGPL3/LFWP LGPL4/LGTA/LUPWAIT /LPBSE/LFRB
O I/O
BVDD BVDD
5,9,29 29
LGPL5 LCLK[0:2] LSYNC_IN LSYNC_OUT
O O I O
BVDD BVDD BVDD BVDD
5,9,29 29 29 29
DMA_DACK[0:1] /GPIO[10:11]
DMA Acknowledge
AD6,AE10
O
OVDD
--
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 11
Pin Map
Table 1. MPC8535E Pinout Listing
Signal DMA_DREQ[0:1] /GPIO[14:15] DMA_DDONE[0:1] /GPIO[12:13] DMA_DREQ[2]/LCS[5] DMA_DACK[2]/LCS[6] DMA_DDONE[2]/LCS[7] DMA_DREQ[3]/IRQ[9] DMA_DACK[3]/IRQ[10] DMA_DDONE[3]/IRQ[11] Signal Name DMA Request DMA Done Package Pin Number AB10,AD11 AA11,AB11 Pin Type I O I/O O O I I/O I/O Power Supply OVDD OVDD BVDD BVDD BVDD OVDD OVDD OVDD Notes -- -- 1,29 1,29 1,29 1 1 1
Chips selects / DMA Request H16 Chips selects / DMA Ack Chips selects / DMA Done External interrupt/DMA request External interrupt/DMA Ack J16 L18 AE13 AD13
External interrupt/DMA done AD14 USB Port 1
USB1_D[7:0] USB1_NXT USB1_DIR USB1_STP USB1_PWRFAULT USB1_PCTL0/GPIO[6] USB1_PCTL1/GPIO[7] USB1_CLK
USB1 Data bits USB1 Next data USB1 Data Direction USB1 Stop USB1 bus power fault. USB1 Port control 0 USB1 Port control 1 USB1 bus clock
AF1,AE2,AE1,AD2, AC2,AC1,AB2,AB1 AF2 AH1 AG1 AH2 AC3 AC4 AD1 USB Port 2
I/O I I O I O O I
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
-- -- -- 5,9 -- -- -- --
USB2_D[7:0] USB2_NXT USB2_DIR USB2_STP USB2_PWRFAULT USB2_PCTL0/GPIO[8] USB2_PCTL1/GPIO[9] USB2_CLK
USB2 Data bits USB2 Next data USB2 Data Direction USB2 Stop USB2 bus power fault. USB2 Port control 0 USB2 Port control 1 USB2 bus clock
AE6,AC6,AF5,AE5, AF4,AE4,AE3,AD3 AC7 AF7 AD7 AC8 AG9 AC9 AD5 --
I/O I I O I O O I
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
-- -- -- 5,9 -- -- -- --
Reserved Reserved
-- --
AH8 AH7,AG6,AH6,AG5, AG4,AH4,AG3,AH3, AG7, AG8, AH9,AH5
-- --
-- --
-- 27
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 12 Freescale Semiconductor
Pin Map
Table 1. MPC8535E Pinout Listing
Signal Signal Name Package Pin Number Pin Type Power Supply Notes
Programmable Interrupt Controller MCP UDE IRQ[0:8] Machine check processor Unconditional debug event External interrupts Y14 AB14 AG22,AF17,AB23, AF19,AG17,AF16, AA22,Y19,AB22 AE13 AD13 I I I OVDD OVDD OVDD -- -- --
IRQ[9]/DMA_DREQ[3] IRQ[10]/DMA_DACK[3] IRQ[11]/DMA_DDONE[3] IRQ_OUT
External interrupt/DMA request External interrupt/DMA Ack
I I/O I/O O
OVDD OVDD OVDD OVDD
1 1 1 2,4
External interrupt/DMA done AD14 Interrupt output AC17
Ethernet Management Interface EC_MDC EC_MDIO Management data clock Management data In/Out Y10 Y11 O I/O OVDD OVDD 5,9,22 --
Gigabit Reference Clock EC_GTX_CLK125 Reference clock AA6 I LVDD 31
Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_TXD[7:0] TSEC1_TX_EN TSEC1_TX_ER TSEC1_TX_CLK TSEC1_GTX_CLK TSEC1_CRS TSEC1_COL TSEC1_RXD[7:0] TSEC1_RX_DV TSEC1_RX_ER TSEC1_RX_CLK Transmit data Transmit Enable Transmit Error Transmit clock In Transmit clock Out Carrier sense Collision detect Receive data Receive data valid Receive data error Receive clock AA8,AA5,Y8,Y5,W3, W5,W4,W6 W1 AB5 AB4 W2 AA9 AB6 AB3,AB7,AB8,Y6,AA2, Y3,Y1,Y2 AA1 Y9 AA3 O O O I O I/O I I I I I LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD 5,9,22 23 5,9 -- -- 17 -- -- -- -- --
Three-Speed Ethernet Controller (Gigabit Ethernet 3) TSEC3_TXD[7:0] TSEC3_TX_EN TSEC3_TX_ER Transmit data Transmit Enable Transmit Error T12,V8,U8,V9,T8,T7, T5,T6 V5 U9 O O O LVDD LVDD LVDD 5,9,22 23 5,9
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 13
Pin Map
Table 1. MPC8535E Pinout Listing
Signal TSEC3_TX_CLK TSEC3_GTX_CLK TSEC3_CRS TSEC3_COL TSEC3_RXD[7:0] TSEC3_RX_DV TSEC3_RX_ER TSEC3_RX_CLK Signal Name Transmit clock In Transmit clock Out Carrier sense Collision detect Receive data Receive data valid Receive data error Receive clock Package Pin Number U10 U5 T10 T9 U12,U13,U6,V6,V1,U3, U2,V3 V2 T4 U1 IEEE 1588 TSEC_1588_CLK TSEC_1588_TRIG_IN[0:1] Clock In Trigger In W9 W8,W7 U11,W10 V10 V11 T11 eSDHC SDHC_CMD SDHC_CD/GPIO[4] SDHC_DAT[0:3] SDHC_DAT[4:7] / SPI_CS[0:3] SDHC_CLK SDHC_WP/GPIO[5] Command line Card detection Data line AH10 AH11 AG12,AH12,AH13, AG11 I/O I I/O I/O I/O I OVDD OVDD OVDD OVDD OVDD OVDD 29 -- 29 29 29 1, 32 I I O O O O LVDD LVDD LVDD LVDD LVDD LVDD 29 29 5,9,29 5,9,29 5,9,29 5,9,29 Pin Type I O I/O I I I I I Power Supply LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD Notes -- -- 17 -- -- -- -- --
TSEC_1588_TRIG_OUT[0:1] Trigger Out TSEC_1588_CLK_OUT TSEC_1588_PULSE_OUT1 TSEC_1588_PULSE_OUT2 Clock Out Pulse Out1 Pulse Out2
8-bit MMC Data line / SPI chip AE8,AC10,AF9,AA10 select SD/MMC/SDIO clock Card write protection AG13 AG10 eSPI
SPI_MOSI SPI_MISO SPI_CLK SPI_CS[0:3] / SDHC_DAT[4:7]
Master Out Slave In Master In Slave Out eSPI clock
AF8 AD9 AD8
I/O I I/O I/O
OVDD OVDD OVDD OVDD
29 29 29 29
eSPI chip select / SDHC 8-bit AE8,AC10,AF9,AA10 MMC data DUART
UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1]
Clear to send Ready to send Receive data
AE11,Y12 AB12,AD12 AC12,AF12
I O I
OVDD OVDD OVDD
29 29 29
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 14 Freescale Semiconductor
Pin Map
Table 1. MPC8535E Pinout Listing
Signal UART_SOUT[0:1] Signal Name Transmit data Package Pin Number AF10,AA12 I2C interface IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA Serial clock Serial data Serial clock Serial data AG21 AH22 AH15 AG14 SerDes1(x4) SD1_TX[7:4] SD1_TX[7:4] SD1_RX[7:4] SD1_RX[7:4] Reserved Reserved SD1_PLL_TPD SD1_REF_CLK SD1_REF_CLK Reserved Reserved -- Transmit Data (+) Transmit Data(-) Receive Data(+) Receive Data(-) -- -- PLL test point Digital PLL Reference clock PLL Reference clock complement -- Y23,W21,V23,U21 Y22,W20,V22,U20 AC28,AB26,AA28,Y26 AC27,AB25,AA27,Y25 R21,P23,N21,M23, R20,P22,N20,M22 T26,R28,P26,N28, T25,R27,P25,N27 V28 U28 U27 T22 T23 SerDes2(x1) SD2_TX[0] SD2_TX[0] SD2_RX[0] SD2_RX[0] Reserved Reserved SD2_PLL_TPD SD2_REF_CLK SD2_REF_CLK Reserved Reserved Transmit data(+) Transmit data(-) Receive data(+) Receive data(-) -- -- PLL test point Digital PLL Reference clock PLL Reference clock complement -- -- P11 P12 P6 P7 M11,M12 N8, N9 L7 M6 M7 L8 L9 O O I I -- -- O I I -- -- X2VDD X2VDD X2VDD X2VDD -- -- X2VDD X2VDD X2VDD X2VDD X2VDD -- -- -- -- 18 34 18 -- -- 18 18 O O I I -- -- O I I -- -- XVDD XVDD XVDD XVDD -- -- XVDD XVDD XVDD -- -- -- -- -- -- 18 33 18 -- -- 18 18 I/O I/O I/O I/O OVDD OVDD OVDD OVDD 4,21,29 4,21,29 4,21,29 4,21,29 Pin Type O Power Supply OVDD Notes 5,9,22, 10,29
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 15
Pin Map
Table 1. MPC8535E Pinout Listing
Signal Signal Name Package Pin Number Pin Type Power Supply Notes
General-Purpose Input/Output GPIO[0:1]/PCI1_REQ[3:4] GPIO[2:3]/PCI1_GNT[3:4] GPIO[4]/SDHC_CD GPIO[5]/SDHC_WP GPIO[6]/USB1_PCTL0 GPIO[7]/USB1_PCTL1 GPIO[8]/USB2_PCTL0 GPIO[9]/USB2_PCTL1 GPIO[10:11] /DMA_DACK[0:1] GPIO[12:13] /DMA_DDONE[0:1] GPIO[14:15] /DMA_DREQ[0:1] GPIO/PCI request GPIO/PCI grant GPIO/SDHC card detection Y15,AE15 AA15,AC14 AH11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD -- -- -- 32 -- -- -- -- -- -- --
GPIO/SDHC write protection AG10 GPIO/USB1 PCTL0 GPIO/USB1 PCTL1 GPIO/USB2 PCTL0 GPIO/USB2 PCTL1 GPIO/DMA Ack GPIO/DMA done GPIO/DMA request AC3 AC4 AG9 AC9 AD6,AE10 AA11,AB11 AB10,AD11 System Control
HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT
Hard reset Hard reset - request Soft reset CheckStop in CheckStop Output
AG16 AG15 AG19 AG18 AH17 Debug
I O I I O
OVDD OVDD OVDD OVDD OVDD
-- 22 -- -- 2,4
TRIG_IN TRIG_OUT/READY /QUIESCE MSRCID[0:1] MSRCID[2:4] MDVAL CLK_OUT
Trigger in Trigger out/Ready/Quiesce
W19 V19
I O O O O O
OVDD OVDD OVDD OVDD OVDD OVDD
-- 22 6,9 6,9,22 6,22 11
Memory debug source port ID W12,W13 Memory debug source port ID V12, W14,W11 Memory debug data valid Clock Out V13 W15 Clock
RTC SYSCLK DDRCLK
Real time clock System clock / PCI clock DDR clock
AF15 AH14 AC13 JTAG
I I I
OVDD OVDD OVDD
-- -- 30
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 16 Freescale Semiconductor
Pin Map
Table 1. MPC8535E Pinout Listing
Signal TCK TDI TDO TMS TRST Signal Name Test clock Test data in Test data out Test mode select Test reset Package Pin Number AG28 AH28 AF28 AH27 AH21 DFT L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL L1 test clock L2 test clock LSSD Mode Test select AA21 AA20 AC25 AA13 Power Management ASLEEP POWER_OK POWER_EN Asleep Power OK Power enable AG20 AC26 AE27 Power and Ground Signals OVDD General I/O supply Y18,AG2,AD4,AB16, AF6,AC18,AB13,AD10, AE14,AD16,AD25, AF27,AE22,AF11, AF20,AF24 -- AA7, AA4 -- OVDD -- O I O OVDD OVDD OVDD 9,16,22 -- -- I I I I OVDD OVDD OVDD OVDD 19 19 19 19 Pin Type I I O I I Power Supply OVDD OVDD OVDD OVDD OVDD Notes -- 12 11 12 12
PVDD LVDD
-- GMAC 1 I/O supply
-- Power for TSEC1 interfaces Power for TSEC3 interfaces Power for DDR DRAM I/O
3.3 V LVDD
-- --
TVDD
GMAC 3 I/O supply
V4,U7
TVDD
--
GVDD
SSTL2 DDR supply
B1,B11,C7,C9,C14, C17,D4,D6,R3,D15,E2, E8,C24,E18,F5,E14, C21,G3,G7,G9,G11, H5,H12,E22,F15,J10, K3,K12,K14,H14,D20, E11,M1,N5 L23,J18,J23,J19,F20, F23,H26,J21 M27,N25,P28,R24, R26,T24,T27,U25, W24,W26,Y24,Y27, AA25,AB28,AD27
GVDD
--
BVDD SVDD
Local bus I/O supply SerDes 1 core logic supply
Power for Local Bus --
BVDD SVDD
-- --
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 17
Pin Map
Table 1. MPC8535E Pinout Listing
Signal XVDD Signal Name SerDes 1 transceiver supply Package Pin Number M21,N23,P20,R22,T20, U23,V21,W22,Y20, AA23 R6,N7,M9 R11,N12,L11 P13,U16,L16,M15,N14, R14,P15,N16,M13, U14,T13,L14,T15,R16, K13 T19,T17,V17,U18,R18, N18,M19,P19,P17,M17 AH16 AH18 AH19 C28 AH20 W28 T1 V15 W17 D5,AE7,F4,D26,D23, C12,C15,E20,D8,B10, AF3,E3,J14,K21,F8,A3, F16,E12,E15,D17,L1, F21,H1,G13,G15,G18, C6,A14,A7,G25,H4, C20,J12,J15,J17,F27, M5,J27,K11,L26,K7, K8,T14,V14,M16,M18, P14,N15,N17,N19,N2, P5,P16,P18,M14,R15, R17,R19,T16,T18,L17, U15,U17,U19,V18,C27, Y13,AE26,AA19,AE21, B28,AC11,AD19,AD23, L15,AD15,AG23,AE9, A27,V7,Y7,AC5,U4,Y4, AE12,AB9,AA14,N13, R13,L13 M20,M24,N22,P21, R23,T21,U22,V20, W23, Y21 Pin Type -- Power Supply XVDD Notes --
S2VDD X2VDD VDD_CORE
SerDes 2 core logic supply SerDes 2 transceiver supply Core, L2 logic supply
-- -- --
S2VDD X2VDD VDD_CORE
-- -- --
VDD_PLAT AVDD_CORE AVDD_PLAT AVDD_DDR AVDD_LBIU AVDD_PCI1 AVDD_SRDS AVDD_SRDS2 SENSEVDD_CORE SENSEVDD_PLAT GND
Platform logic supply CPU PLL supply Platform PLL supply DDR PLL supply Local Bus PLL supply PCI PLL supply SerDes 1 PLL supply SerDes 2 PLL supply -- -- Ground
-- -- -- -- -- -- -- -- -- -- --
VDD_PLAT AVDD_CORE AV DD_PLAT AVDD_DDR AVDD_LBIU AVDD_PCI1 AV DD_SRDS AVDD_SRDS2 VDD_CORE VDD_PLAT --
-- 20,28 20 20 20 20 20 20 13 13 --
XGND
SerDes 1Transceiver pad GND (xpadvss)
--
--
--
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 18 Freescale Semiconductor
Pin Map
Table 1. MPC8535E Pinout Listing
Signal SGND Signal Name SerDes 1 Transceiver core logic GND (xcorevss) Package Pin Number M28,N26,P24,P27, R25,T28,U24,U26,V24, W25,Y28,AA24,AA26, AB24,AB27,AD28 R12,M10,N11,L12 P8,P9,N6,M8 V27 T2 V16 Analog Signals MVREF SSTL2 reference voltage A28 Reference voltage for DDR -- -- -- -- -- -- -- -- GVDD/2 -- Pin Type -- Power Supply -- Notes --
X2GND S2GND AGND_SRDS AGND_SRDS2 SENSEVSS
SerDes 2 Transceiver pad GND (xpadvss) SerDes 2 Transceiver core logic GND (xcorevss) SerDes 1 PLL GND SerDes 2 PLL GND GND Sensing
-- -- -- -- --
-- -- -- -- --
-- -- -- -- 13
SD1_IMP_CAL_RX SD1_IMP_CAL_TX SD1_PLL_TPA SD2_IMP_CAL_RX SD2_IMP_CAL_TX SD2_PLL_TPA Reserved Reserved
Rx impedance calibration Tx impedance calibration PLL test point analog Rx impedance calibration Tx impedance calibration PLL test point analog -- --
M26 AE28 V26 R7 L6 T3 R4 R5
200 (1%) to GND 100 (1%) to GND AVDD_SRD S analog 200 (1%) to GND 100 (1%) to GND AVDD_SRD S2 analog -- --
-- -- 18 -- -- 18 -- --
No Connect Pins NC -- C19,D7,D10,L10,R10, B6,F12,J7,P10,M25, W27,N24,N10,R8,J9, K9,V25,R9 -- -- --
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 19
Pin Map
Table 1. MPC8535E Pinout Listing
Signal Signal Name Package Pin Number Pin Type Power Supply Notes
Notes: 1. All multiplexed signals may be listed only once and may not re-occur. 2. Recommend a weak pull-up resistor (2-10 K) be placed on this pin to OVDD. 3. This pin must always be pulled-high. 4. This pin is an open drain signal. 5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 6. Treat these pins as no connects (NC) unless using debug address functionality. 7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k pull-up or pull-down resistors. See Section 22.2, "CCB/SYSCLK PLL Ratio." 8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-k pull-up or pull-down resistors. See the Section 22.3, "e500 Core PLL Ratio." 9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan. 10.For proper state of these signals during reset, UART_SOUT[1] must be pulled down to GND through a resistor. UART_SOUT[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down the value of the net at reset, then a pullup is needed on UART_SOUT[0]. 11.This output is actively driven during reset rather than being three-stated during reset. 12.These JTAG pins have weak internal pull-up P-FETs that are always enabled. 13.These pins are connected to the VDD_CORE/V DD_PLAT/GND planes internally and may be used by the core power supply to improve tracking and regulation. 15. These pins have other manufacturing or debug test functions. It's recommended to add both pull-up resistor pads to OVDD and pull-down resistor pads to GND on board to support future debug testing when needed. 16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset. 17. This pin is only an output in FIFO mode when used as Rx Flow Control. 18. Do not connect. 19.These must be pulled up (100 - 1 k) to OVDD. 20. Independent supplies derived from board VDD. 21. Recommend a pull-up resistor (1 K) be placed on this pin to OVDD. 22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0], EC_MDC, TSEC1_TXD[3], TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. 23. This pin requires an external 4.7-k pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 24. General-Purpose POR configuration of user system.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 20 Freescale Semiconductor
Overall DC Electrical Characteristics
Table 1. MPC8535E Pinout Listing
Signal Signal Name Package Pin Number Pin Type Power Supply Notes
25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as "No Connect" or terminated through 2-10 K pull-up resistors with the default of internal arbiter if the address pins are not connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter--through POR config pins--irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI device connected on the bus. 26.MDIC[0] is grounded through an 18.2- (full-strength mode) or 36.4- (half-strength mode) precision 1% resistor and MDIC[1] is connected to GVDD through an 18.2- (full-strength mode) or 36.4- (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR IOs. 27.Connect to GND through a pull down 1 k resistor. 28. It must be the same as VDD_CORE 29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when GCR[DEEPSLEEP_Z] =1. 30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E PowerQUICCTM III Integrated Host Processor Family Reference Manual Rev.0, Table 4-3 in section 4.2.2 "Clock Signals", section 4.4.3.2 "DDR PLL Ratio" and Table 4-10 "DDR Complex Clock PLL Ratio" for more detailed description regarding DDR controller operation in asynchronous and synchronous modes. 31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND. 32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for SD/MMC card specification. 33. Must connect to XGND. 34. Must connect to X2GND
2
2.1
Electrical Characteristics
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings1
Characteristic Symbol VDD_CORE VDD_PLAT AVDD_CORE AVDD SVDD, S2VDD XVDD, X2VDD Max Value -0.3 to 1.21 -0.3 to 1.1 -0.3 to 1.21 -0.3 to 1.1 -0.3 to 1.1 -0.3 to 1.1 Unit Notes V V V V V V -- -- -- -- -- --
Table 2 provides the absolute maximum ratings.
Core supply voltage Platform supply voltage PLL core supply voltage PLL other supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers and PCI Express
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 21
Overall DC Electrical Characteristics
Table 2. Absolute Maximum Ratings1 (continued)
Characteristic DDR SDRAM Controller I/O supply voltage DDR2 SDRAM Interface DDR3 SDRAM Interface LVDD (eTSEC1) TVDD (eTSEC3) PCI, DUART, system control and power management, I2C, USB, eSDHC, eSPI and JTAG I/O voltage Local bus I/O voltage OVDD BVDD Symbol GVDD Max Value -0.3 to 1.98 -0.3 to 1.65 -0.3 to 3.63 -0.3 to 2.75 -0.3 to 3.63 -0.3 to 2.75 -0.3 to 3.63 -0.3 to 3.63 -0.3 to 2.75 -0.3 to 1.98 -0.3 to (GVDD + 0.3) -0.3 to (GVDD + 0.3) -0.3 to (LVDD + 0.3) -0.3 to (TVDD + 0.3) -0.3 to (BVDD + 0.3) -0.3 to (OVDD + 0.3) -55 to 150 V V V V 2 2 -- -- Unit Notes V --
Three-speed Ethernet I/O, MII management voltage
Input voltage
DDR2/DDR3 DRAM signals DDR2/DDR3 DRAM reference Three-speed Ethernet signals Local bus signals PCI, DUART, SYSCLK, system control and power management, I2C, and JTAG signals
MVIN MVREF LV IN TV IN BV IN OVIN TSTG
V V V -- V
0C
3 -- 3 -- 3 --
Storage temperature range
Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. The 3.63-V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V maximum applies. See Section 2.9.2, "FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications," for details on the recommended operating conditions per protocol. 3. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
2.1.2
Recommended Operating Conditions
Table 3 provides the recommended operating conditions for this device. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 3. Recommended Operating Conditions
Characteristic Core supply voltage Platform supply voltage PLL core supply voltage PLL other supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers and PCI Express Symbol VDD_CORE VDD_PLAT AVDD_CORE AVDD SVDD XVDD Recommended Value Unit Notes 1.0 50 mV 1.0 50 mV 1.0 50 mV 1.0 50 mV 1.0 50 mV 1.0 50 mV V V V V V V -- -- 2 2 -- --
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 22 Freescale Semiconductor
Overall DC Electrical Characteristics
Table 3. Recommended Operating Conditions (continued)
Characteristic DDR2 SDRAM Interface DDR SDRAM Controller I/O supply DDR3 SDRAM Interface voltage Three-speed Ethernet I/O voltage Symbol GVDD Recommended Value Unit Notes 1.8 V 90 mV 1.5 V 75 mV LVDD (eTSEC1) TVDD (eTSEC3) PCI, DUART, system control and power management, I2C, USB, eSDHC, eSPI and JTAG I/O voltage Local bus I/O voltage OVDD BVDD 3.3 V 165 mV 2.5 V 125 mV 3.3 V 165 mV 2.5 V 125 mV 3.3 V 165 mV 3.3 V 165 mV 2.5 V 125 mV 1.8 V 90 mV GND to GV DD GVDD/2 1% GND to LVDD GND to TVDD GND to BVDD GND to OV DD TA= 0 (min) to TJ= 90(max) TA TJ TA= 0 (min) to TJ= 105 (max) TA= -40 (min) to TJ= 105 (max) C 6 V V 4 -- V 5 V 3
Input voltage
DDR2 and DDR3 SDRAM Interface signals DDR2 and DDR3 SDRAM Interface reference Three-speed Ethernet signals Local bus signals PCI, Local bus, DUART, SYSCLK, system control and power management, I2C, and JTAG signals
MVIN MVREF LV IN TVIN BVIN OVIN
V V V V V
3 -- 5 -- 4
Operating Temperature range
Commercial Industrial standard temperature range Extended temperature range
Notes: 2. This voltage is the input to the filter discussed in Section 3.2.1, "PLL Power Supply Filtering," and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter. 3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. Minimum temperature is specified with TA; maximum temperature is specified with TJ.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 23
Overall DC Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8535E.
B/G/L/OV DD + 20% B/G/L/OVDD + 5% VIH B/G/L/OVDD
GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of tCLOCK1
Note: 1. tCLOCK refers to the clock period associated with the respective interface: For I2C and JTAG, tCLOCK references SYSCLK. For DDR, tCLOCK references MCLK. For eTSEC, tCLOCK references EC_GTX_CLK125. For eLBC, tCLOCK references LCLK. For PCI, tCLOCK references PCI1_CLK or SYSCLK. 2. With the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
Figure 7. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD The core voltage must always be provided at nominal 1.0 V (See Table 2 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface uses differential receivers referenced by the externally supplied MVREFn signal (nominally set to GVDD/2) as is appropriate for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 24 Freescale Semiconductor
Power Sequencing
2.1.3
Output Driver Characteristics
Table 4. Output Drive Capability
Driver Type Programmable Output Impedance () 25 35 45(default) 45(default) 125 Supply Voltage BVDD = 3.3 V BVDD = 2.5 V BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V OVDD = 3.3 V GVDD = 1.8 V GVDD = 1.5 V LVDD = 2.5/3.3 V OVDD = 3.3 V OVDD = 3.3 V 2 Notes 1
Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Local bus interface utilities signals
PCI signals
25 42 (default)
DDR2 signal DDR3 signal TSEC signals DUART, system control, JTAG I2C
16 32 (half strength mode) 20 40 (half strength mode) 42 42 150
3 2 -- -- --
Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset. 3. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at Tj = 105C and at GVDD (min)
2.2
1. 2. 3.
Power Sequencing
VDD_PLAT, VDD_CORE (if POWER_EN is not used to control VDD_CORE), AVDD, BVDD, LVDD, OVDD, SVDD,S2V DD, TVDD, XVDD and X2VDD [Wait for POWER_EN to assert], then VDD_CORE (if POWER_EN is used to control VDD_CORE) GVDD
The MPC8535E requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up:
All supplies must be at their stable values within 50 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required. From a system standpoint, if any of the I/O power supplies ramp prior to the VDD platform supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 25
Power Characteristics
2.3
Power Characteristics
Table 5. MPC8535E Power Dissipation 5
The estimated power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III devices is shown in Table 5.
Core CCB DDR VDD Frequen Frequen Frequen Platfor Power Mode m cy cy cy (MHz) Maximum (A) Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) Maximum (A) Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) Maximum (A) Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) 1000 400 400 1.0 800 400 400 1.0 600 400 400 1.0 (MHz) (MHz) (V)
VDD Core (V)
Junction Tempera ture (C) 105 /90
Core Power mean7 -- -- 1.5
Platform Power9 Notes mean7 -- -- 1.5 1.4 1.4 1.0 0.6 -- -- 1.5 1.4 1.4 1.0 0.6 -- -- 1.5 1.4 1.4 1.0 0.6
Max 4.1/3.3 3.7/2.9 -- 1.9 1.5 1.5 0 4.5/3.7 3.9/3.1 -- 2.1 1.5 1.5 0 4.8/4.0 4.1/3.3 -- 2.2 1.6 1.6 0
Max 4.7/3.7 4.7/3.7 -- 1.9 1.9 1.6 1.1 4.7/3.7 4.7/3.7 -- 1.9 1.9 1.6 1.1 4.7/3.7 4.7/3.7 -- 1.9 1.9 1.6 1.1 1, 3, 8 1, 4, 8 1, 2 1 1 1 6 1, 3, 8 1, 4, 8 1, 2 1 1 1 1,6 1, 3, 8 1, 4, 8 1, 2 1 1 1 1, 6
1.0
65
1.2 0.8 0.8
35 105 / 90
0 -- -- 1.7
1.0
65
1.3 0.8 0.8
35 105 / 90
0 -- -- 1.9
1.0
65
1.4 0.8 0.8
35
0
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 26 Freescale Semiconductor
Power Characteristics
Table 5. MPC8535E Power Dissipation (continued)5
VDD DDR CCB Core Frequen Frequen Frequen Platfor Power Mode cy cy m cy (MHz) Maximum (A) Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) 35 1250 500 500 1.0 1.0 (MHz) (MHz) (V) VDD Core (V) Junction Tempera ture (C) 105 / 90 65 Core Power mean7 -- -- 2.2 1.6 0.8 0.8 0 2.4 1.6 1.6 0 Platform Power9 Notes Max 5.3/4.4 4.4/3.6 mean7 -- -- 1.7 1.5 1.5 1.1 0.6 2.1 2.1 1.7 1.2 Max 5.0/4.0 5.0/4.0 1, 3, 8 1, 4, 8 1 1 1 1 1, 6
Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (VDD) and 65C junction temperature (see Table 3) while running the Dhrystone benchmark. 3. Maximum power is the maximum power measured with the worst process and recommended core and platform voltage (VDD) at maximum operating junction temperature (see Table 3) while running a smoke test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy. 4. Thermal power is the maximum power measured with worst case process and recommended core and platform voltage (V DD) at maximum operating junction temperature (see Table 3) while running the Dhrystone benchmark. 6. Maximum power is the maximum number measured with USB1, eTSEC1, and DDR blocks enabled. The Mean power is the mean power measured with only external interrupts enabled and DDR in self refresh. 7. Mean power is provided for information purposes only and is the mean power consumed by a statistically significant range of devices. 8. Maximum operating junction temperature (see Table 3) for Commercial Tier is 90 0C, for Industrial Tier is 105 0C. 9. Platform power is the power supplied to all the V DD_PLAT pins.
See Section 2.23.6.1, "SYSCLK to Platform Frequency Options," for the full range of CCB frequencies that MPC8535E supports.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 27
Input Clocks
2.4
2.4.1
Input Clocks
System Clock Timing
Table 6. SYSCLK AC Timing Specifications
Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8535E.
At recommended operating conditions (see Table 2) with OVDD = 3.3 V 165 mV. Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Symbol fSYSCLK tSYSCLK tKH, tKL tKHK/tSYSCLK -- Min 33 7.5 0.6 40 -- Typical -- -- 1.0 -- -- Max 133 30 2.1 60 +/-150 Unit MHz ns ns % ps Notes 1 -- 2 -- 3, 4
Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies. See Section 2.23.2, "CCB/SYSCLK PLL Ratio," and Section 2.23.3, "e500 Core PLL Ratio," for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V. 3. The SYSCLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. 4. For spread spectrum clocking, guidelines are +0% to -1% down spread at a modulation rate between 20 KHz and 60 KHz on SYSCLK.
2.4.2
PCI Clock Timing
When the PCI controller is configured for asynchronous operation, the reference clock for the PCI controller is not the SYSCLK input, but instead the PCI_CLK. Table 7 provides the PCI reference clock AC timing specifications for the MPC8535E. Table 7. PCICLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V 165 mV. Parameter/Condition PCICLK frequency PCICLK cycle time PCICLK rise and fall time PCICLK duty cycle Symbol fPCICLK tPCICLK tKH, tKL tKHK/tPCICLK Min 33 15 0.6 40 Typical -- -- 1.0 -- Max 66 30 2.1 60 Unit MHz ns ns % Notes -- -- 1 --
Notes: 1. Rise and fall times for PCICLK are measured at 0.6 V and 2.7 V.
2.4.3
Real Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 x tCCB, and minimum clock low time is 2 x tCCB. There is no minimum RTC frequency; RTC may be grounded if not needed.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 28 Freescale Semiconductor
Input Clocks
2.4.4
eTSEC Gigabit Reference Clock Timing
Table 8. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition Symbol fG125 tG125 tG125R/tG125F Min -- -- -- Typical 125 8 -- 0.75 1.0 tG125H/tG125 45 47 -- 55 53 % 2 Max -- -- Unit MHz ns ns Notes -- -- 1
Table 8 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the MPC8535E.
EC_GTX_CLK125 frequency EC_GTX_CLK125 cycle time EC_GTX_CLK rise and fall time LV DD, TVDD = 2.5V LV DD, TVDD = 3.3V EC_GTX_CLK125 duty cycle GMII, TBI 1000Base-T for RGMII, RTBI
Notes: 1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD=2.5V, and from 0.6 and 2.7V for L/TVDD=3.3V at 0.6 V and 2.7 V. 2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC GTX_CLK. See Section 2.9.2.6, "RGMII and RTBI AC Timing Specifications," for duty cycle for 10Base-T and 100Base-T reference clock.
2.4.5
DDR Clock Timing
Table 9. DDRCLK AC Timing Specifications
Table 9 provides the DDR clock (DDRCLK) AC timing specifications for the MPC8535E.
At recommended operating conditions with OVDD of 3.3V 5%. Parameter/Condition DDRCLK frequency DDRCLK cycle time DDRCLK rise and fall time DDRCLK duty cycle DDRCLK jitter Symbol fDDRCLK tDDRCLK tKH, tKL tKHK/tDDRCLK -- Min 66 6.0 0.6 40 -- Typical -- -- 1.0 -- -- Max 166 15.15 1.2 60 +/- 150 Unit MHz ns ns % ps Notes 1 -- 2 -- 3, 4
Notes: 1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex clock frequency does not exceed the maximum or minimum operating frequencies. See Section 2.23.4, "DDR/DDRCLK PLL Ratio," for ratio settings. 2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V. 3. The DDRCLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter. 4. For spread spectrum clocking, guidelines are +0% to -1% down spread at a modulation rate between 20 kHz and 60 kHz on DDRCLK.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 29
RESET Initialization
2.4.6
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. The "platform clock (CCB) frequency" in the following formula refers to the maximum platform (CCB) frequency of the speed bins the part belongs to, which is defined in Table 73. For FIFO GMII mode: FIFO TX/RX clock frequency <= platform clock frequency/3.2 For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz For FIFO encoded mode: FIFO TX/RX clock frequency <= platform clock frequency/3.2 For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz
2.4.7
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document.
2.5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8535E. Table 10 provides the RESET initialization AC timing specifications for the DDR SDRAM component(s). Table 10. RESET Initialization Timing Specifications
Parameter/Condition Required assertion time of HREST Minimum assertion time for SRESET PLL input setup time with stable SYSCLK before HRESET negation Input setup time for POR configurations (other than PLL config) with respect to negation of HRESET Input hold time for all POR configurations (including PLL config) with respect to negation of HRESET Maximum valid-to-high impedance time for actively driven POR configurations with respect to negation of HRESET HRESET rise time Notes: 1. SYSCLK is the primary clock input for the MPC8535E. Min 100 3 100 4 2 -- -- Max -- -- -- -- -- 5 1 Unit s Sysclk s SYSCLKs SYSCLKs SYSCLKs SYSCLK Notes -- 1 -- 1 1 1 --
Table 11 provides the PLL lock times. Table 11. PLL Lock Times
Parameter/Condition PLL lock times Local bus PLL PCI bus lock time Min -- -- -- Max 100 50 50 Unit s s s Notes -- -- --
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 30 Freescale Semiconductor
DDR2 and DDR3 SDRAM
2.6
DDR2 and DDR3 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8535E. Note that DDR2 SDRAM is GVDD(type) = 1.8 V and DDR3 SDRAM is GVDD(type) = 1.5 V.
2.6.1
DDR2 and DDR3 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8535E when interfacing to DDR2 SDRAM. Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) Symbol GVDD MV REF VTT VIH VIL IOZ IOH IOL Min 1.7 0.49 x GVDD MVREF - 0.04 MV REF+ 0.125 -0.3 -50 -13.4 13.4 Max 1.9 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MVREF - 0.125 50 -- -- Unit V V V V V A mA mA Notes 1 2 3 -- -- 4 -- --
Notes: 1. GVDD is expected to be within 50 mV of the DRAM GV DD at all times. 2. MVREF is expected to be equal to 0.5 x GV DD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 13 provides the recommended operating conditions for the DDR SDRAM Controller of the MPC8535E when interfacing to DDR3 SDRAM. Table 13. DDR3 SDRAM Interface DC Electrical Characteristics for GVDD(typ) = 1.5 V
Parameter/Condition I/O supply voltage I/O reference voltage Input high voltage Input low voltage Output leakage current Symbol GVDD MVREFn VIH VIL IOZ Min 1.425 0.49 x GVDD MVREFn + 0.100 GND -50 Max 1.575 0.51 x GVDD GVDD MVREFn - 0.100 50 Unit V V V V A Notes 1 2 -- -- 3
Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREFn is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREFn may not exceed 1% of the DC value. 3. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 31
DDR2 and DDR3 SDRAM
Table 14 provides the DDR capacitance when GVDD(type) = 1.8 V. Table 14. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1, 2 1, 2
Note: 1. This parameter is sampled. GVDD = 1.8 V 0.090 V (for DDR2), f = 1 MHz, TA = 25C, VOUT = GV DD/2, VOUT (peak-to-peak) = 0.2 V. 2. This parameter is sampled. GVDD = 1.5 V 0.075 V (for DDR3), f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.175 V.
Table 15 provides the current draw characteristics for MVREF. Table 15. Current Draw Characteristics for MVREF
Parameter/Condition Current draw for MVREFn DDR2 SDRAM DDR3 SDRAM Symbol IMVREFn Min -- Max 1500 1250 Unit A Note 1
1.The voltage regulator for MVREF must be able to supply up to 500 A or 1250 uA current for DDR2 or DDR3 respectively.
2.6.2
DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM Controller interface. The DDR controller supports both DDR2 and DDR3 memories. Please note that although the minimum data rate for most off-the-shelf DDR3 DIMMs available is 800 MHz, JEDEC specification does allow the DDR3 to run at the data rate as low as 606 MHz. Unless otherwise specified, the AC timing specifications described in this section for DDR3 is applicable for data rate between 606 MHz and 667 MHz, as long as the DC and AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications as well as the specifications and requirements described in this MPC8535E hardware specifications document.
2.6.2.1
DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Table 16 through Table 18 provide the input AC timing specifications for the DDR controller.
At recommended operating conditions with GVDD of 1.8 V 5%
Parameter AC input low voltage 667 <=533 AC input high voltage 667 <=533
Symbol VILAC
Min -- --
Max MVREF - 0.20 MVREF - 0.25 -- --
Unit V V V V
VIHAC
MVREF + 0.20 MVREF + 0.25
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 32 Freescale Semiconductor
DDR2 and DDR3 SDRAM
Table 17. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface
At recommended operating conditions with GVDD of 1.5 V 5%. DDR3 data rate is between 606MHz and 667MHz.
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- MVREF + 0.175
Max MV REF - 0.175 --
Unit V V
Notes -- --
Table 18. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.
Parameter Controller Skew for MDQS--MDQ/MECC 667 MHz 533 MHz 400 MHz
Symbol tCISKEW -- -- --
Min -- -240 -300 -365
Max -- 240 300 365
Unit ps -- -- --
Notes 1, 2 3 -- --
Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW =+/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 3. Maximum DDR2 and DDR3 frequency is 667MHz.
3F
igure 8 shows the DDR2 and DDR3 SDRAM interface input timing diagram.
MCK[n] MCK[n] tMCK
MDQS[n]
MDQ[x]
D0 tDISKEW
D1 tDISKEW
Figure 8. DDR SDRAM Input Timing Diagram
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 33
DDR2 and DDR3 SDRAM
2.6.2.2
DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
Table 19. DDR SDRAM Output AC Timing Specifications
Table 19 contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.
At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.
Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing ADDR/CMD output setup with respect to MCK 667 MHz 533 MHz 400 MHz ADDR/CMD output hold with respect to MCK 667 MHz 533 MHz 400 MHz MCS[n] output setup with respect to MCK 667 MHz 533 MHz 400 MHz MCS[n] output hold with respect to MCK 667 MHz 533 MHz 400 MHz MCK to MDQS Skew <= 667 MHz MDQ/MECC/MDM output setup with respect to MDQS 667 MHz 533 MHz 400 MHz MDQ/MECC/MDM output hold with respect to MDQS 667 MHz 533 MHz 400 MHz MDQS preamble start
Symbol 1 tMCK tDDKHAS
Min 3.0
Max 5
Unit ns ns
Notes 2 3 7
1.10 1.48 1.95 tDDKHAX 1.10 1.48 1.95 tDDKHCS 1.10 1.48 1.95 tDDKHCX 1.10 1.48 1.95 tDDKHMH -0.6 tDDKHDS, tDDKLDS 450 538 700 tDDKHDX, tDDKLDX 450 538 700 tDDKHMP
-- -- -- ns -- -- -- ns -- -- -- ns -- -- -- ns 0.6 ps -- -- -- ps -- -- -- ns
3 7
3 7
3 7
4 7 5 7
5 7
6
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 34 Freescale Semiconductor
DDR2 and DDR3 SDRAM
Table 19. DDR SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.
Parameter <= 667 MHz MDQS epilogue end <= 667 MHz
Symbol 1
Min 0.9 x tMCK
Max
Unit
Notes 7
tDDKHME 0.4 x tMCK 0.6 x tMCK
ns
6 7
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8536E PowerQUICCTM III Integrated Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. 7. Maximum DDR2 and DDR3 frequency is 667 MHz
NOTE For the ADDR/CMD setup and hold specifications in Table 19, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 35
DDR2 and DDR3 SDRAM
Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns
MDQS tDDKHMH(min) = -0.6 ns
MDQS
Figure 9. Timing Diagram for tDDKHMH Figure 10 shows the DDR SDRAM output timing diagram.
MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP
Figure 10. DDR SDRAM Output Timing Diagram
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 36 Freescale Semiconductor
eSPI
Figure 11 provides the AC test load for the DDR bus.
Output Z0 = 50 GVDD/2
RL = 50
Figure 11. DDR AC Test Load
2.7
eSPI
This section describes the DC and AC electrical specifications for the eSPI of the MPC8535E.
2.7.1
eSPI DC Electrical Characteristics
Table 20. SPI DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = -6.0 mA IOL = 6.0 mA IOL = 3.2 mA -- -- 0 V VIN OVDD Min 2.4 -- -- 2.0 -0.3 -- Max -- 0.5 0.4 OVDD + 0.3 0.8 10 Unit V V V V V A
Table 20 provides the DC electrical characteristics for the device eSPI.
2.7.2
eSPI AC Timing Specifications
Table 21. SPI AC Timing Specifications1
Characteristic Symbol 2 tNIKHOX tNIKHOX tNIKHOV tNIKHOV tNIKHOX2 Min 0.5 4.0 -- -- 0 Max -- -- 6.0 7.4 -- Unit ns ns ns Note -- 3 3 -- --
Table 21 and provide the eSPI input and output AC timing specifications.
SPI_MOSI output--Master data (internal clock) hold time SPI_MOSI output--Master data (internal clock) delay SPI_CS outputs--Master data (internal clock) hold time
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 37
eSPI
Table 21. SPI AC Timing Specifications1 (continued)
Characteristic SPI_CS outputs--Master data (internal clock) delay SPI inputs--Master data (internal clock) input setup time SPI inputs--Master data (internal clock) input hold time Symbol 2 tNIKHOV2 tNIIVKH tNIIXKH Min -- 5 0 Max 6.0 -- -- Unit ns ns ns Note -- -- --
Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V). 3. The greater of the two output timings for tNIKHOX and tNIKHOV are used when the SPCOM[RxDelay] bit of eSPI Command Register is set. For example, the tNIKHOX is 4.0 and tNIKHOV is 7.4 if SPCOM[RxDelay] is set to be 1.
Figure 12 provides the AC test load for the SPI.
Output Z0 = 50 OVDD/2
RL = 50
Figure 12. SPI AC Test Load Figure 13 represent the AC timing from Table 21. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 13 shows the SPI timing in Master mode (internal clock).
SPICLK (output) tNIIVKH tNIIXKH
Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note)
tNIKHOX tNIKHOV
tNIKHOV2 Output Signals: SPI_CS[0:3] (See Note) Note: The clock edge is selectable on SPI.
tNIKHOX2
Figure 13. SPI AC Timing in Master mode (Internal Clock) Diagram
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 38 Freescale Semiconductor
DUART
2.8
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8535E.
2.8.1
DUART DC Electrical Characteristics
Table 22. DUART DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = VDD) High-level output voltage (OV DD = min, IOH = -2 mA) Low-level output voltage (OV DD = min, IOL = 2 mA) Symbol VIH VIL IIN VOH VOL Min 2 - 0.3 -- 2.4 -- Max OV DD + 0.3 0.8 5 -- 0.4 Unit V V A V V
Table 22 provides the DC electrical characteristics for the DUART interface.
Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
2.8.2
DUART AC Electrical Specifications
Table 23. DUART AC Timing Specifications
Parameter Minimum baud rate Maximum baud rate Oversample rate Value CCB clock/1,048,576 CCB clock/16 16 Unit baud baud -- Notes 2 2,3 4
Table 23 provides the AC timing parameters for the DUART interface.
Notes: 2. CCB clock refers to the platform clock. 3. Actual attainable baud rate will be limited by the latency of interrupt processing. 4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample.
2.9
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 39
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
2.9.1
Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps) -- FIFO/GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics
The electrical characteristics specified here apply to all FIFO mode, gigabit media independent interface (GMII), media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and management data clock (MDC), and serial gigabit media independent interface (SGMII). The RGMII, RTBI and FIFO mode interfaces are defined for 2.5 V, while the GMII, MII, RMII, and TBI interfaces can operate at 3.3V. The GMII, MII, or TBI interface timing is compliant with IEEE 802.3. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 2.10, "Ethernet Management Interface Electrical Characteristics." The electrical characteristics for SGMII is specified in Section 2.9.3, "SGMII Interface Electrical Characteristics." The SGMII interface conforms (with exceptions) to the Serial-GMII Specification Version 1.8.
2.9.1.1
GMII, MII, TBI, RGMII, RMII and RTBI DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 24 and Table 25. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. Table 24. GMII, MII, RMII, and TBI DC Electrical Characteristics
Parameter Supply voltage 3.3 V Output high voltage (LVDD/TVDD = Min, IOH = -4.0 mA) Output low voltage (LVDD/TVDD = Min, IOL = 4.0 mA) Input high voltage Input low voltage Input high current (V IN = LVDD, VIN = TVDD) Input low current (V IN = GND) Notes:
1 2
Symbol LVDD TVDD VOH VOL VIH VIL IIH IIL
Min 3.13 2.40 GND 1.90 -0.3 -- -600
Max 3.47 LV DD/TVDD + 0.3 0.50 LV DD/TVDD + 0.3 0.90 40 --
Unit V V V V V A A
Notes
1, 2
-- -- -- --
1, 2,3
3
LV DD supports eTSECs 1. TVDD supports eTSECs 3. 3 The symbol VIN, in this case, represents the LV IN and TVIN symbols referenced in Table 1 and Table 2.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 40 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 25. RGMII, RTBI, and FIFO DC Electrical Characteristics
Parameters Supply voltage 2.5 V Output high voltage (LV DD/TVDD = Min, IOH = -1.0 mA) Output low voltage (LV DD/TVDD = Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (VIN = LVDD, V IN = TVDD) Input low current (VIN = GND) Note:
1 2
Symbol LVDD/TVDD VOH VOL VIH VIL IIH IIL
Min 2.37 2.00 GND - 0.3 1.70 -0.3 -- -15
Max 2.63 LVDD/TVDD + 0.3 0.40 LVDD/TVDD + 0.3 0.70 10 --
Unit V V V V V A A
Notes
1,2
-- -- -- --
1, 2,3 3
LVDD supports eTSECs 1. TVDD supports eTSECs 3. 3 Note that the symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2. IN IN IN
2.9.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section.
2.9.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC's FIFO modes is the double data rate RGMII and RTBI specifications, since they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and source clock in GMII fashion. When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn's TSECn_TX_CLK, while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a sourcesynchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and the platform speed. For more information see Section 2.4.6, "Platform to FIFO Restrictions." A summary of the FIFO AC specifications appears in Table 26 and Table 27. Table 26. FIFO Mode Transmit AC Timing Specification
Parameter/Condition TX_CLK, GTX_CLK clock period2 TX_CLK, GTX_CLK duty cycle TX_CLK, GTX_CLK peak-to-peak jitter Symbol tFIT tFITH tFITJ Min 6.0 45 -- Typ 8.0 50 -- Max 100 55 250 Unit ns % ps
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Table 26. FIFO Mode Transmit AC Timing Specification (continued)
Parameter/Condition Rise time TX_CLK (20%-80%) Fall time TX_CLK (80%-20%) GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time Symbol tFITR tFITF tFITDX1 Min -- -- 0.5 Typ -- -- -- Max 0.75 0.75 3.0 Unit ns ns ns
Note: 1. Data valid tFITDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max Hold) 2. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, "Platform to FIFO Restrictions," for more detailed description.
Table 27. FIFO Mode Receive AC Timing Specification
Parameter/Condition RX_CLK clock period1 RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%-80%) Fall time RX_CLK (80%-20%) RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK Symbol tFIR tFIRH/tFIRH tFIRJ tFIRR tFIRF tFIRDV tFIRDX Min 6.0 45 -- -- -- 1.5 0.5 Typ 8.0 50 -- -- -- -- -- Max 100 55 250 0.75 0.75 -- -- Unit ns % ps ns ns ns ns
Note: 1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, "Platform to FIFO Restrictions," for more detailed description.
Timing diagrams for FIFO appear in Figure 14 and Figure 15.
.
tFITF tFIT
tFITR
GTX_CLK
tFITH tFITDV tFITDX
TXD[7:0] TX_EN TX_ER
Figure 14. FIFO Transmit AC Timing Diagram
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 42 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management tFIRR tFIR
RX_CLK
tFIRH tFIRF
RXD[7:0] RX_DV RX_ER
valid data
tFIRDV tFIRDX
Figure 15. FIFO Receive AC Timing Diagram
2.9.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
2.9.2.2.1
GMII Transmit AC Timing Specifications
Table 28. GMII Transmit AC Timing Specifications
Table 28 provides the GMII transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition GTX_CLK clock period GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK data clock rise time (20%-80%) GTX_CLK data clock fall time (80%-20%)
Symbol 1 tGTK tGTKHDX3 tGTXR tGTXF
Min -- 0.5 -- --
Typ 8.0 -- -- --
Max -- 5.0 1.0 1.0
Unit ns ns ns ns
Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Data valid tGTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time Max Hold)
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 43
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Figure 16 shows the GMII transmit AC timing diagram.
tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTKHDV tGTXF tGTXR
Figure 16. GMII Transmit AC Timing Diagram
2.9.2.2.2
GMII Receive AC Timing Specifications
Table 29. GMII Receive AC Timing Specifications
Table 29 provides the GMII receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise (20%-80%) RX_CLK clock fall time (80%-20%)
Symbol 1 tGRX tGRXH/tGRX tGRDVKH tGRDXKH tGRXR tGRXF
Min -- 35 2.0 0 -- --
Typ 8.0 -- -- -- -- --
Max -- 65 -- -- 1.0 1.0
Unit ns ns ns ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 17 provides the AC test load for eTSEC.
Output Z0 = 50 LVDD/2
RL = 50
Figure 17. eTSEC AC Test Load
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 44 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 18 shows the GMII receive AC timing diagram.
tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF tGRXR
Figure 18. GMII Receive AC Timing Diagram
2.9.2.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
2.9.2.3.1
MII Transmit AC Timing Specifications
Table 30. MII Transmit AC Timing Specifications
Table 30 provides the MII transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise (20%-80%) TX_CLK data clock fall (80%-20%)
Symbol 1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR tMTXF
Min -- -- 35 1 1.0 1.0
Typ 400 40 -- 5 -- --
Max -- -- 65 15 4.0 4.0
Unit ns ns % ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 45
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 19 shows the MII transmit AC timing diagram.
tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR
Figure 19. MII Transmit AC Timing Diagram
2.9.2.3.2
MII Receive AC Timing Specifications
Table 31. MII Receive AC Timing Specifications
Table 31 provides the MII receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise (20%-80%) RX_CLK clock fall time (80%-20%)
Symbol 1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF
Min -- -- 35 10.0 10.0 1.0 1.0
Typ 400 40 -- -- -- -- --
Max -- -- 65 -- -- 4.0 4.0
Unit ns ns % ns ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 20 provides the AC test load for eTSEC.
Output Z0 = 50 LVDD/2
RL = 50
Figure 20. eTSEC AC Test Load
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 46 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 21 shows the MII receive AC timing diagram.
tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKL tMRXF Valid Data tMRXR
Figure 21. MII Receive AC Timing Diagram
2.9.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
2.9.2.4.1
TBI Transmit AC Timing Specifications
Table 32. TBI Transmit AC Timing Specifications
Table 32 provides the TBI transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to TCG[9:0] delay time GTX_CLK rise (20%-80%) GTX_CLK fall time (80%-20%)
Symbol 1 tTTX tTTXH/tTTX tTTKHDX2 tTTXR tTTXF
Min -- 40 1.0 -- --
Typ 8.0 -- -- -- --
Max -- 60 5.0 1.0 1.0
Unit ns % ns ns ns
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Data valid tTTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max Hold)
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 47
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 22 shows the TBI transmit AC timing diagram.
tTTX GTX_CLK tTTXH tTTXF TCG[9:0] tTTKHDV tTTKHDX tTTXR tTTXF tTTXR
Figure 22. TBI Transmit AC Timing Diagram
2.9.2.4.2
TBI Receive AC Timing Specifications
Table 33. TBI Receive AC Timing Specifications
Table 33 provides the TBI receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition2 Clock period for TBI Receive Clock 0, 1 Skew for TBI Receive Clock 0, 1 Duty cycle for TBI Receive Clock 0, 1 RCG[9:0] setup time to rising edge of TBI Receive Clock 0, 1 RCG[9:0] hold time to rising edge of TBI Receive Clock 0, 1 Clock rise time (20%-80%) for TBI Receive Clock 0, 1 Clock fall time (80%-20%) for TBI Receive Clock 0, 1
Symbol 1 tTRX tSKTRX tTRXH/tTRX tTRDVKH tTRDXKH tTRXR tTRXF
Min -- 7.5 40 2.5 1.5 0.7 0.7
Typ 16.0 -- -- -- -- -- --
Max -- 8.5 60 -- -- 2.4 2.4
Unit ns ns % ns ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. The signals "TBI Receive Clock 0" and "TBI Receive Clock 1" refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively. These two clock signals are also referred as PMA_RX_CLK[0:1].
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 23 shows the TBI receive AC timing diagram.
tTRX TBI Receive Clock 1 (TSECn_TX_CLK) tTRXH RCG[9:0] tTRDVKH tSKTRX TBI Receive Clock 0 (TSECn_RX_CLK) tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Valid Data Valid Data tTRXR
Figure 23. TBI Receive AC Timing Diagram
2.9.2.5
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface. In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn pin (no receive clock is used on in this mode, whereas for the dual-clock mode this is the PMA0 receive clock). The 125-MHz transmit clock is applied on the in all TBI modes. A summary of the single-clock TBI mode AC specifications for receive appears in Table 34. Table 34. TBI single-clock Mode Receive AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 3.3 V 5%
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%-80%) Fall time RX_CLK (80%-20%) RCG[9:0] setup time to RX_CLK rising edge RCG[9:0] hold time to RX_CLK rising edge
Symbol tTRR tTRRH tTRRJ tTRRR tTRRF tTRRDV tTRRDX
Min 7.5 40 -- -- -- 2.0 1.0
Typ 8.0 50 -- -- -- -- --
Max 8.5 60 250 1.0 1.0 -- --
Unit ns % ps ns ns ns ns
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 49
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
A timing diagram for TBI receive appears in Figure 24.
.
tTRRR tTRR
RX_CLK
tTRRH RCG[9:0] tTRRF
valid data
tTRRDV tTRRDX
Figure 24. TBI Single-Clock Mode Receive AC Timing Diagram
2.9.2.6
RGMII and RTBI AC Timing Specifications
Table 35. RGMII and RTBI AC Timing Specifications
Table 35 presents the RGMII and RTBI AC timing specifications.
At recommended operating conditions with L/TVDD of 2.5 V 5%.
Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period duration
3 2
Symbol 1 tSKRGT_TX tSKRGT_RX tRGT tRGTH/tRGT
3, 4
Min -500 1.0 7.2 45 40 -- --
Typ 0 -- 8.0 -- 50 -- --
Max 500 2.8 8.8 55 60 0.75 0.75
Unit ps ns ns % % ns ns
Duty cycle for 1000BASE-T4 Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%-80%) Fall time (20%-80%)
tRGTH/tRGT tRGTR tRGTF
Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transition to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 50 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 25 shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT_TX TXD[8:5][3:0] TXD[7:4][3:0] TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT_TX TX_CLK (At PHY)
TX_CTL
RXD[8:5][3:0] RXD[7:4][3:0]
RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT_RX RXD[4] RXDV RXD[9] RXERR tSKRGT_RX
RX_CTL
RX_CLK (At PHY)
Figure 25. RGMII and RTBI AC Timing and Multiplexing Diagrams
2.9.2.7
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
2.9.2.7.1
RMII Transmit AC Timing Specifications
Table 36. RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in Table 36.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition TSECn_TX_CLK clock period TSECn_TX_CLK duty cycle TSECn_TX_CLK peak-to-peak jitter
Symbol 1 tRMT tRMTH tRMTJ
Min 15.0 35 --
Typ 20.0 50 --
Max 25.0 65 250
Unit ns % ps
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Table 36. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition Rise time TSECn_TX_CLK (20%-80%) Fall time TSECn_TX_CLK (80%-20%) TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay
Symbol 1 tRMTR tRMTF tRMTDX
Min 1.0 1.0 2.0
Typ -- -- --
Max 2.0 2.0 10.0
Unit ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 26 shows the RMII transmit AC timing diagram.
tRMT TSECn_TX_CLK tRMTH TXD[1:0] TX_EN TX_ER tRMTDX tRMTF tRMTR
Figure 26. RMII Transmit AC Timing Diagram
2.9.2.7.2
RMII Receive AC Timing Specifications
Table 37. RMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition TSECn_RX_CLK clock period TSECn_RX_CLK duty cycle TSECn_RX_CLK peak-to-peak jitter Rise time TSECn_RX_CLK (20%-80%)
Symbol 1 tRMR tRMRH tRMRJ tRMRR
Min 15.0 35 -- 1.0
Typ 20.0 50 -- --
Max 25.0 65 250 2.0
Unit ns % ps ns
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Table 37. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition Fall time TSECn_RX_CLK (80%-20%) RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge RXD[1:0], CRS_DV, RX_ER hold time to TSECn_RX_CLK rising edge
Symbol 1 tRMRF tRMRDV tRMRDX
Min 1.0 4.0 2.0
Typ -- -- --
Max 2.0 -- --
Unit ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 27 provides the AC test load for eTSEC.
Output Z0 = 50 LVDD/2
RL = 50
Figure 27. eTSEC AC Test Load Figure 28 shows the RMII receive AC timing diagram.
tRMR TSECn_RX_CLK tRMRH RXD[1:0] CRS_DV RX_ER tRMRDV tRMRDX tRMRF Valid Data tRMRR
Figure 28. RMII Receive AC Timing Diagram
2.9.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of MPC8535E as shown in Figure 29, where CTX is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential pair features 50- output impedance. Each input of the SerDes receiver differential pair features 50- on-die termination to S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in Figure 68. When an eTSEC port is configured to operate in SGMII mode, the parallel interface's output signals of this eTSEC port can be left floating. The input signals should be terminated based on the guidelines described in Section 3.6, "Connection Recommendations," as long as such termination does not violate the desired POR configuration requirement on these pins, if applicable.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 53
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference clock is required on SD2_REF_CLK and SD2_REF_CLK pins.
2.9.3.1
DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.20, "High-Speed Serial Interfaces."
2.9.3.2
AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
Table 38 lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source. Table 38. SD2_REF_CLK and SD2_REF_CLK AC Requirements
Symbol tREF tREFCJ tREFPJ REFCLK cycle time REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles Phase jitter. Deviation in edge location with respect to mean edge location Parameter Description Min -- -- -50 Typical 10 (8) -- -- Max -- 100 50 Units Notes ns ps ps 1 -- 2,3
Notes: 1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR. 2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter "Dj" should be less than or equal to 50 ps.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 54 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
2.9.3.3
SGMII Transmitter and Receiver DC Electrical Characteristics
Table 39 and Table 40 describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) as depicted in Figure 30. Table 39. SGMII DC Transmitter Electrical Characteristics
Parameter Supply Voltage Output high voltage Output low voltage Output ringing Symbol X2VDD VOH VOL VRING Min 0.95 -- X2VDD-Typ/2 |VOD|-max/2 -- 323 296 269 Output differential voltage2, 3, 5 |VOD| 243 215 189 162 Output offset voltage Output impedance (single-ended) Mismatch in a pair Change in VOD between "0" and "1" Change in VOS between "0" and "1" Output current on short to GND VOS RO RO |VOD| VOS ISA, ISB 425 40 -- -- -- -- Typ 1.0 -- -- -- 500 459 417 376 333 292 250 500 -- -- -- -- -- Max 1.05 X2V DD-Typ/2 + |VOD|-max/2 -- 10 725 665 604 545 483 424 362 575 60 10 25 25 40 mV % mV mV mA Unit V mV mV % Notes -- 1 1 -- Equalization setting: 1.0x Equalization setting: 1.09x Equalization setting: 1.2x mV Equalization setting: 1.33x Equalization setting: 1.5x Equalization setting: 1.71x Equalization setting: 2.0x 1, 4 -- -- -- -- --
Notes: 1. This will not align to DC-coupled SGMII. X2VDD-Typ=1.0V. 2. |VOD| = |VSD2_TXn - V SD2_TXn|. |VOD| is also referred as output differential peak voltage. V TX-DIFFp-p = 2*|VOD|. 3. The |VOD| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of MPC8535E's SerDes 2 Control Register: * The MSbit (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude - power up default); * The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table. 4. VOS is also referred to as output common mode voltage. * 5.The |VOD| value shown in the Typ column is based on the condition of X2VDD-Typ=1.0V, no common mode offset variation (VOS =550mV), SerDes2 transmitter is terminated with 100- differential load between SD2_TX[n] and SD2_TX[n].
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 55
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
50 SD2_TXn
CTX
SD_RXm 50
Transmitter 50 SD2_TXn MPC8535E SGMII SerDes Interface SD2_RXn 50 CTX SD_RXm
Receiver
50 50
CTX
SD_TXm
Receiver
Transmitter 50
50
SD2_RXn
CTX
SD_TXm
Figure 29. 4-Wire AC-Coupled SGMII Serial Link Connection Example
MPC8535E SGMII SerDes Interface 50 SD2_TXn Transmitter 50 SD2_TXn 50
50 Vos VOD
Figure 30. SGMII Transmitter DC Measurement Circuit Table 40. SGMII DC Receiver Electrical Characteristics
Parameter Supply Voltage DC Input voltage range Input differential voltage LSTS = 0 LSTS = 1 Symbol X2VDD -- VRX_DIFFp-p 100 175 Min 0.95 Typ 1.0 N/A -- -- 1200 Max 1.05 Unit V -- mV Notes -- 1 2, 4
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 40. SGMII DC Receiver Electrical Characteristics (continued)
Parameter Loss of signal threshold LSTS = 0 LSTS = 1 Input AC common mode voltage Receiver differential input impedance Receiver common mode input impedance Common mode input voltage VCM_ACp-p ZRX_DIFF ZRX_CM VCM Symbol VLOS Min 30 65 -- 80 20 -- Typ -- -- -- 100 -- Vxcorevss Max 100 175 100 120 35 -- mV V 5 -- -- 6 Unit mV Notes 3, 4
Notes: 1. Input must be externally AC-coupled. 2. VRX_DIFFp-p is also referred to as peak to peak input differential voltage 3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. See PCI Express Differential Receiver (RX) Input Specifications section for further explanation. 4. The LSTS shown in the table refers to the LSTSA or LSTSE bit field of MPC8535E's SerDes 2 Control Register. 5. VCM_ACp-p is also referred to as peak to peak AC common mode voltage. 6. On-chip termination to S2GND (xcorevss).
2.9.3.4
SGMII AC Timing Specifications
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver inputs (SD2_RX[n] and SD2_RX[n]) as depicted in Figure 32 respectively.
2.9.3.4.1
SGMII Transmit AC Timing Specifications
Table 41. SGMII Transmit AC Timing Specifications
Table 41 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.
At recommended operating conditions with X2VDD = 1.0V 5%.
Parameter Deterministic Jitter Total Jitter Unit Interval VOD fall time (80%-20%) VOD rise time (20%-80%) Notes: 1. Each UI is 800 ps 100 ppm.
Symbol JD JT UI tfall trise
Min -- -- 799.92 50 50
Typ -- -- 800 -- --
Max 0.17 0.35 800.08 120 120
Unit UI p-p UI p-p ps ps ps
Notes -- -- 1 -- --
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
2.9.3.4.2
SGMII Receive AC Timing Specifications
Table 42 provides the SGMII receive AC timing specifications. Source synchronous clocking is not supported. Clock is recovered from the data. Figure 31 shows the SGMII Receiver Input Compliance Mask eye diagram. Table 42. SGMII Receive AC Timing Specifications
At recommended operating conditions with X2VDD = 1.0V 5%.
Parameter Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Sinusoidal Jitter Tolerance Total Jitter Tolerance Bit Error Ratio Unit Interval AC Coupling Capacitor
Symbol JD JDR JSIN JT BER UI CTX
Min 0.37 0.55 0.1 0.65 -- 799.92 5
Typ -- -- -- -- -- 800 --
Max -- -- -- -- 10-12 800.08 200
Unit UI p-p UI p-p UI p-p UI p-p
Notes 1 1 1 1 --
ps nF
2 3
Notes: 1. Measured at receiver. 2. Each UI is 800 ps 100 ppm. 3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.
VRX_DIFFp-p-max/2
Receiver Differential Input Voltage
VRX_DIFFp-p-min/2
0 - VRX_DIFFp-p-min/2
- V RX_DIFFp-p-max/2
0
0.275
0.4
Time (UI)
0.6
0.725
1
Figure 31. SGMII Receiver Input Compliance Mask
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 58 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 32. SGMII AC Test/Measurement Load
2.9.4
eTSEC IEEE 1588 AC Specifications
tT1588CLKOUT tT1588CLKOUTH TSEC_1588_CLK_OUT tT1588OV TSEC_1588_PULSE_OUT TSEC_1588_TRIG_OUT
Figure 33 shows the data and command output timing diagram.
Figure 33. eTSEC IEEE 1588 Output AC timing
1
The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is count starting falling edge.
Figure 34 provides the data and command input timing diagram.
tT1588CLK tT1588CLKH TSEC_1588_CLK
TSEC_1588_TRIG_IN tT1588TRIGH
Figure 34. eTSEC IEEE 1588 Input AC timing
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 59
Ethernet Management Interface Electrical Characteristics
The IEEE 1588 AC timing specifications are in Table 43. Table 43. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition TSEC_1588_CLK clock period TSEC_1588_CLK duty cycle
Symbol tT1588CLK tT1588CLKH /tT1588CLK tT1588CLKINJ tT1588CLKINR tT1588CLKINF tT1588CLKOUT tT1588CLKOTH /tT1588CLKOUT tT1588OV tT1588TRIGH
Min 3.8 40 -- 1.0 1.0 2*tT1588CLK 30 0.5 2*tT1588CLK_MAX
Typ -- 50 -- -- -- -- 50 -- --
Max TTX_CLK*7 60 250 2.0 2.0 -- 70 3.0 --
Unit ns % ps ns ns ns % ns ns
Note 1 --
TSEC_1588_CLK peak-to-peak jitter Rise time eTSEC_1588_CLK (20%-80%) Fall time eTSEC_1588_CLK (80%-20%) TSEC_1588_CLK_OUT clock period TSEC_1588_CLK_OUT duty cycle
-- -- -- -- --
TSEC_1588_PULSE_OUT TSEC_1588_TRIG_IN pulse width
-- 2
Note: 1. When TMR_CTRL[CKSEL]=00, the external TSEC_1588_CLK input is selected as the 1588 timer reference clock source, with the timing defined in the Table above. The maximum value of tT1588CLK is defined in terms of TTX_CLK, which is the maximum clock cycle period of the equivalent interface speed that the eTSEC1 port is running. When eTSEC1 is configured to operate in the parallel mode, the TTX_CLK is the maximum clock period of the TSEC1_TX_CLK. When eTSEC1 operates in SGMII mode, the maximum value of tT1588CLK is defined in terms of the recovered clock from SGMII SerDes. For example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns respectively. See the MPC8536E PowerQUICCTM III Integrated Communications Processor Reference Manual for a description of TMR_CTRL registers. 2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8536E PowerQUICCTM III Integrated Processor Reference Manual for a description of TMR_CTRL registers.
2.10
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals EC_MDIO (management data input/output) and EC_MDC (management data clock). The electrical characteristics for GMII, SGMII, RGMII, RMII, TBI and RTBI are specified in Section 2.9, "Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management"
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 60 Freescale Semiconductor
Ethernet Management Interface Electrical Characteristics
2.10.1
MII Management DC Electrical Characteristics
The EC_MDC and EC_MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for EC_MDIO and EC_MDC are provided in Table 44. Table 44. MII Management DC Electrical Characteristics
Parameter Supply voltage (3.3 V) Output high voltage (OVDD = Min, IOH = -1.0 mA) Output low voltage (OVDD =Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (OVDD = Max, VIN 1 = 2.1 V) Input low current (OVDD = Max, VIN = 0.5 V) Symbol OVDD VOH VOL VIH VIL IIH IIL Min 3.13 2.10 GND 2.0 -- -- -600 Max 3.47 OVDD + 0.3 0.50 -- 0.90 40 -- Unit V V V V V A A
Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
2.10.2
MII Management AC Electrical Specifications
Table 45. MII Management AC Timing Specifications
Table 45 provides the MII management AC timing specifications.
At recommended operating conditions with OVDD is 3.3 V 5%.
Parameter/Condition EC_MDC frequency EC_MDC period EC_MDC clock pulse width high EC_MDC to EC_MDIO delay EC_MDIO to EC_MDC setup time
Symbol 1 fMDC tMDC tMDCH tMDKHDX tMDDVKH
Min 0.74 120 32 (16 * tplb_clk)-3 5
Typ 2.5 400 -- -- --
Max 8.3 1350 -- (16 * tplb_clk)+3 --
Unit MHz ns ns ns ns
Notes 2 -- -- 3,5,6 --
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 61
USB
Table 45. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V 5%.
Parameter/Condition EC_MDIO to EC_MDC hold time EC_MDC rise time EC_MDC fall time
Symbol 1 tMDDXKH tMDCR tMDHF
Min 0 -- --
Typ -- -- --
Max -- 10 10
Unit ns ns ns
Notes -- -- --
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (fCCB). The actual EC_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of MPC8535E's MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, fMDC = 533/(2*4*8) = 533/64 = 8.3 MHz. That is, for a system running at a particular platform frequency (fCCB), the EC_MDC output clock frequency can be programmed between maximum fMDC = fCCB/64 and minimum fMDC = fCCB/448. See the MPC8536E reference manual's MIIMCFG register section for more detail. 3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods +/-3ns. For example, with a platform clock of 333MHz, the min/max delay is 48ns +/-3ns. Similarly, if the platform clock is 400MHz, the min/max delay is 40ns +/-3ns). 5. tCLKplb_clk is the platform (CCB) clock 6. EC_MDC to EC_MDIO Data valid tMDKHDV is a function of clock period and max delay time tMDKHDX. (Min Setup = Cycle time - Max Hold)
Figure 35 shows the MII management AC timing diagram.
tMDC EC_MDC tMDCH EC_MDIO (Input) tMDDVKH tMDDXKH EC_MDIO (Output) tMDKHDX tMDCF tMDCR
Figure 35. MII Management Interface Timing Diagram
2.11
USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8535E.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 62 Freescale Semiconductor
USB
2.11.1
USB DC Electrical Characteristics
Table 46. USB DC Electrical Characteristics
Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- OVDD - 0.2 -- Max OVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V
Table 46 provides the DC electrical characteristics for the USB interface.
High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A
Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
2.11.2 USB AC Electrical Specifications
Table 47 describes the general timing parameters of the USB interface of the MPC8535E. Table 47. USB General Timing Parameters
Parameter usb clock cycle time Input setup to usb clock - all inputs input hold to usb clock - all inputs usb clock to output valid - all outputs Output hold from usb clock - all outputs Symbol 1 tUSCK tUSIVKH tUSIXKH tUSKHOV tUSKHOX Min 15 4 1 -- 2 Max -- -- -- 7 -- Unit ns ns ns ns ns Notes 2-5 2-5 2-5 2-5 2-5
Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes usb timing (US) for the input (I) to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to USB clock. 3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification.
Figure 36 and Figure 37 provide the AC test load and signals for the USB, respectively.
Output Z0 = 50 OVDD/2
RL = 50
Figure 36. USB AC Test Load
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 63
USB
USB0_CLK/USB1_CLK/DR_CLK tUSIVKH Input Signals tUSIXKH
tUSKHOV Output Signals:
tUSKHOX
Figure 37. USB Signals
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 64 Freescale Semiconductor
enhanced Local Bus Controller (eLBC)
2.12
enhanced Local Bus Controller (eLBC)
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8535E.
2.12.1
Local Bus DC Electrical Characteristics
Table 48. Local Bus DC Electrical Characteristics (3.3 V DC)
Parameter Symbol BVDD VIH VIL IIN VOH VOL Min 3.13 1.9 -0.3 -- 2.4 -- Max 3.47 BVDD + 0.3 0.8 5 -- 0.4 Unit V V V A V V
Table 48 provides the DC electrical characteristics for the local bus interface operating at BVDD = 3.3 V DC.
Supply voltage 3.3V High-level input voltage Low-level input voltage Input current (BVIN 1 = 0 V or BVIN = BV DD) High-level output voltage (BVDD = min, IOH = -2 mA) Low-level output voltage (BVDD = min, IOL = 2 mA)
Note: 1. Note that the symbol BV IN, in this case, represents the BV IN symbol referenced in Table 1.
Table 49 provides the DC electrical characteristics for the local bus interface operating at BVDD = 2.5 V DC. Table 49. Local Bus DC Electrical Characteristics (2.5 V DC)
Parameter Supply voltage 2.5V High-level input voltage Low-level input voltage Input current (BVIN 1 = 0 V or BVIN = BVDD) High-level output voltage (BVDD = min, IOH = -1 mA) Low-level output voltage (BVDD = min, IOL = 1 mA) Symbol BVDD VIH VIL IIH IIL VOH VOL 2.0 GND - 0.3 Min 2.37 1.70 -0.3 -- Max 2.63 BVDD + 0.3 0.7 10 -15 BVDD + 0.3 0.4 V V Unit V V V A
Note: 1. Note that the symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1.
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enhanced Local Bus Controller (eLBC)
Table 50 provides the DC electrical characteristics for the local bus interface operating at BVDD = 1.8 V DC. Table 50. Local Bus DC Electrical Characteristics (1.8 V DC)
Parameter Supply voltage 1.8V High-level input voltage Low-level input voltage Input current (BVIN 1 = 0 V or BVIN = BVDD) High-level output voltage Symbol BVDD VIH VIL IIN Condition -- -- -- -- IOH = -100 A VOH IOH = -2 mA IOH = 100 A Low-level output voltage VOL IOH = 2 mA Min 1.71 0.65*BVDD -0.3 -15 BVDD - 0.2 BVDD - 0.45 -- -- Max 1.89 0.3+BVDD 0.35*BVDD 10 -- -- 0.2 0.45 V V Unit V V V A
Note: 1. Note that the symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1.
2.12.2
Local Bus AC Electrical Specifications
Table 51 describes the general timing parameters of the local bus interface at BV DD = 3.3 V DC. For information about the frequency range of local bus see Section 2.23.1, "Clock Ranges." Table 51. Local Bus General Timing Parameters (BVDD = 3.3 V DC)
Parameter Local bus cycle time Local bus duty cycle LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH setup and hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Symbol 1 tLBK tLBKH/tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOV4 tLBKHOX1 1.8 1.7 1.0 1.0 1.5 -- -- -- -- 0.7 Min 7.5 43 Max 12 57 150 -- -- -- -- -- 2.3 2.4 2.3 2.3 -- Unit ns % ps ns ns ns ns ns ns ns ns ns ns Notes 2 -- 7 3, 4 3, 4 3, 4 3, 4 6 -- 3 3 3 3
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enhanced Local Bus Controller (eLBC)
Table 51. Local Bus General Timing Parameters (BVDD = 3.3 V DC) (continued)
Parameter Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Symbol 1 tLBKHOX2 tLBKHOZ1 tLBKHOZ2 Min 0.7 -- -- Max -- 2.5 2.5 Unit ns ns ns Notes 3 5 5
Note: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6.tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed with LBCR[AHD] = 0. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2.
Table 52 describes the general timing parameters of the local bus interface at BV DD = 2.5 V DC. Table 52. Local Bus General Timing Parameters (BVDD = 2.5 V DC)
Parameter Local bus cycle time Local bus duty cycle LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH setup and hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Configuration Symbol 1 -- -- -- -- -- -- -- -- -- -- -- -- -- tLBK tLBKH/tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOV4 tLBKHOX1 Min 7.5 43 -- 1.9 1.8 1.1 1.1 1.5 -- -- -- -- 0.8 Max 12 57 150 -- -- -- -- -- 2.4 2.5 2.4 2.4 -- Unit ns % ps ns ns ns ns ns ns ns ns ns ns Notes 2 -- 7 3, 4 3, 4 3, 4 3, 4 6 -- 3 3 3 3
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 67
enhanced Local Bus Controller (eLBC)
Table 52. Local Bus General Timing Parameters (BVDD = 2.5 V DC) (continued)
Parameter Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Configuration Symbol 1 -- -- -- tLBKHOX2 tLBKHOZ1 tLBKHOZ2 Min 0.8 -- -- Max -- 2.6 2.6 Unit ns ns ns Notes 3 5 5
Note: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 2.5-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed with LBCR[AHD] = 0. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2.
Table 53 describes the general timing parameters of the local bus interface at BV DD = 1.8 V DC Table 53. Local Bus General Timing Parameters (BVDD = 1.8 V DC)
Parameter Local bus cycle time Local bus duty cycle LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH setup and hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Configuration Symbol 1 -- -- -- -- -- -- -- -- -- -- -- -- -- tLBK tLBKH/tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOV4 tLBKHOX1 2.4 1.9 1.1 1.1 1.2 -- -- -- -- 0.9 Min 7.5 43 Max 12 57 150 -- -- -- -- -- 3.2 3.2 3.2 3.2 -- Unit ns % ps ns ns ns ns ns ns ns ns ns ns 7 3, 4 3, 4 3, 4 3, 4 6 -- 3 3 3 3 Notes 2
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 68 Freescale Semiconductor
enhanced Local Bus Controller (eLBC)
Table 53. Local Bus General Timing Parameters (BVDD = 1.8 V DC) (continued)
Parameter Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Configuration Symbol 1 -- -- -- tLBKHOX2 tLBKHOZ1 tLBKHOZ2 Min 0.9 -- -- Max -- 2.6 2.6 Unit ns ns ns Notes 3 5 5
Note: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 1.8-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed with LBCR[AHD] = 0. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2.
Figure 38 provides the AC test load for the local bus. Figure 38. Local Bus AC Test Load
Output Z0 = 50 RL = 50 BVDD/2
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 69
enhanced Local Bus Controller (eLBC)
Figure 39 to Figure 42 show the local bus signals.
LSYNC_IN tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH2 Input Signal: LGTA tLBIXKH2 tLBIXKH1
UPM Mode Input Signal: LUPWAIT tLBKHOV1 Output Signals: LA[27:31]/LBCTL/LOE tLBKHOV2 Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV3 Output (Address) Signal: LAD[0:31]
tLBKHOZ1 tLBKHOX1
tLBKHOZ2 tLBKHOX2
tLBKHOZ2 tLBKHOX2
tLBOTOT tLBKHOV4 LALE
Figure 39. Local Bus Signals, Non-Special Signals Only (PLL Enabled)
NOTE
In PLL bypass mode, some signals are launched and captured on the opposite edge of LCLK[n] to that used in PLL Enable Mode. In this mode, output signals are launched at the falling edge of the LCLK[n] and inputs signals are captured at the rising edge of LCLK[n] with the exception of LGTA/LUPWAIT (which is captured at the falling edge of the LCLK[n]).
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 70 Freescale Semiconductor
enhanced Local Bus Controller (eLBC)
LCLK[n] tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA
tLBIVKL2 tLBIXKL2
tLBIXKH1
UPM Mode Input Signal: LUPWAIT tLBKLOV1 tLBKLOX1 Output Signals: LA[27:31]/LBCTL/LOE tLBKLOV2 Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKLOV3 Output (Address) Signal: LAD[0:31] tLBKLOV4 LALE tLBOTOT tLBKLOX2 tLBKLOZ2 tLBKLOZ1
Figure 40. Local Bus Signals (PLL Bypass Mode) Table 54 describes the general timing parameters of the local bus interface at VDD = 3.3 V DC with PLL disabled. Table 54. Local Bus General Timing Parameters--PLL Bypassed
Parameter Local bus cycle time Local bus duty cycle Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) Symbol 1 tLBK tLBKH/tLBK tLBIVKH1 tLBIVKL2 tLBIXKH1 tLBIXKL2 tLBOTOT tLBKLOV1 Min 12 43 5.1 4.2 -1.4 -2.0 1.4 -- Max -- 57 -- -- -- -- -- 0.5 Unit ns % ns ns ns ns ns ns Notes 2 -- 4, 5 4, 5 4, 5 4, 5 6 4
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 71
enhanced Local Bus Controller (eLBC)
Table 54. Local Bus General Timing Parameters--PLL Bypassed (continued)
Parameter Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD, and LALE Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Symbol 1 tLBKLOV2 tLBKLOV3 tLBKLOV4 tLBKLOX1 tLBKLOX2 tLBKLOZ1 tLBKLOZ2 Min -- -- -- -- -- -- -- Max 0.5 0.5 0.5 2.2 2.2 0.1 0.1 Unit ns ns ns ns ns ns ns Notes 4 4 4 4,8 4,8 7 7
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to local bus clock for PLL bypass mode. 3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2. 4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 3.3-V signaling levels. 5. Input timings are measured at the pin. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed with LBCR[AHD] = 0. 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. These timing parameters for PLL bypass mode are defined in the opposite direction of the PLL enabled output hold timing parameters.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 72 Freescale Semiconductor
enhanced Local Bus Controller (eLBC)
LSYNC_IN
T1 T3 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKHOZ1
GPCM Mode Input Signal: LGTA
tLBIVKH2 UPM Mode Input Signal: LUPWAIT
tLBIXKH2
tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1
tLBIXKH1
Figure 41. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4(PLL Enabled)
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 73
Enhanced Secure Digital Host Controller (eSDHC)
LSYNC_IN
T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKHOZ1
GPCM Mode Input Signal LGTA tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 tLBIXKH1 tLBIXKH2
Input Signals: LAD[0:31]/LDP[0:3] (PLL Bypass Mode) tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5]
tLBKHOZ1
Figure 42. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 8 or 16(PLL Enabled)
2.13
Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface of the MPC8535E.
2.13.1
eSDHC DC Electrical Characteristics
Table 55. eSDHC interface DC Electrical Characteristics
Table 55 provides the DC electrical characteristics for the eSDHC interface of the MPC8535E.
At recommended operating conditions (see Table 3)
Characteristic Input high voltage Input low voltage Input/Output leakage current Output high voltage
Symbol VIH VIL IIN/IOZ VOH
Condition -- -- -- IOH = -100 uA @OVDDmin
Min 0.625 * OVDD -0.3 -10 0.75 * OVDD
Max OVDD+0.3 0.25 * OVDD 10 --
Unit V V uA V
Notes -- -- -- --
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 74 Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
Table 55. eSDHC interface DC Electrical Characteristics (continued)
At recommended operating conditions (see Table 3)
Characteristic Output low voltage Output high voltage Output low voltage
Symbol VOL VOH VOL
Condition IOL = 100uA @OVDDmin IOH = -100 uA IOL = 2 mA
Min -- OVDD - 0.2 --
Max 0.125 * OVDD -- 0.3
Unit V -- --
Notes -- 2 2
Notes: 1. The min V IL and VIH values are based on the respective min and max OVIN values found in Table 3. 2. Open drain mode for MMC cards only.
2.13.2
eSDHC AC Timing Specifications
Table 56. eSDHC AC Timing Specifications
Table 56 provides the eSDHC AC timing specifications as defined in Figure 44.
At recommended operating conditions (see Table 3)
Parameter SD_CLK clock frequency: SD/SDIO Full speed/high speed mode MMC Full speed/high speed mode SD_CLK clock frequency - identification mode SD_CLK clock low time - High speed/Full speed mode SD_CLK clock high time - High speed/Full speed mode SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK Output delay time: SD_CLK to SD_CMD, SD_DATx valid
Symbol1 fSHSCK
Min 0
Max 25/50 20/52 400 -- -- 3 -- -- 3
Unit MHz
Notes 2, 5
fSIDCK tSHSCKL tSHSCKH tSHSCKR/ tSHSCKF tSHSIVKH tSHSIXKH tSHSKHOV
0 100 7/10 7/10 -- 5 2.5 -3
KHz ns ns ns ns ns ns
3, 5 5 5 5 5 4,5 5
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. In full speed mode, clock frequency value can be 0-25 MHz for a SD/SDIO card and 0-20 MHz for a MMC card. In high speed mode, clock frequency value can be 0-50 MHz for a SD/SDIO card and 0-52MHz for a MMC card. 3. 0 Hz means to stop the clock. The given minimum frequency range is for cases were a continuous clock is required. 4. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns. 5. CCARD 10 pF, (1 card), and CL = CBUS + CHOST+CCARD 40 pF
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 75
Programmable Interrupt Controller (PIC)
Figure 43 provides the eSDHC clock input timing diagram.
eSDHC External Clock operational mode
VM
VM
VM tSHSCKL tSHSCKH
tSHSCK VM = Midpoint Voltage (OVDD/2) tSHSCKR tSHSCKF
Figure 43. eSDHC Clock Input Timing Diagram Figure 44 provides the data and command input/output timing diagram.
SD_CK External Clock VM VM tSHSIVKH SD_DAT/CMD Inputs VM tSHSIXKH VM
SD_DAT/CMD Outputs
tSHSKHOV VM = Midpoint Voltage (OVDD/2)
Figure 44. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock
2.14
Programmable Interrupt Controller (PIC)
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods).
2.15
JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8535E.
2.15.1
JTAG DC Electrical Characteristics
Table 57. JTAG DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage Symbol 1 VIH VIL Min 2 -0.3 Max OVDD + 0.3 0.8 Unit V V
Table 57 provides the DC electrical characteristics for the JTAG interface.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 76 Freescale Semiconductor
JTAG
Table 57. JTAG DC Electrical Characteristics (continued)
Parameter Input current (VIN1 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = -2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA) Symbol 1 IIN VOH VOL Min -- 2.4 -- Max 5 -- 0.4 Unit A V V
Notes: 1. Note that the symbol VIN, in this case, represents the OVIN.
2.15.2
JTAG AC Electrical Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8535E. Table 58 provides the JTAG AC timing specifications as defined in Figure 45 through Figure 48. Table 58. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 3).
Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Input hold times: Output Valid times: Output hold times:
Symbol 1 fJTG t JTG tJTKHKL tJTGR & tJTGF tTRST tJTDVKH tJTDXKH tJTKLDV tJTKLDX
Min 0 30 15 0 25 4 10 -- 0
Max 33.3 -- -- 2 -- -- -- 10 --
Unit MHz ns ns ns ns ns ns ns ns
Notes -- -- -- -- 2
3 3
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 3.) The output timings are measured at the pins. All output timings assume a purely resistive 50- load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 77
Serial ATA (SATA)
Figure 45 provides the AC test load for TDO and the boundary-scan outputs.
Output Z0 = 50 OVDD/2
R L = 50
Figure 45. AC Test Load for the JTAG Interface Figure 46 provides the JTAG clock input timing diagram.
JTAG External Clock
VM tJTKHKL tJTG
VM
VM tJTGR tJTGF
VM = Midpoint Voltage (OVDD/2)
Figure 46. JTAG Clock Input Timing Diagram Figure 47 provides the TRST timing diagram.
TRST
VM tTRST
VM
VM = Midpoint Voltage (OVDD/2)
Figure 47. TRST Timing Diagram Figure 48 provides the boundary-scan timing diagram.
JTAG External Clock
VM tJTDVKH
VM tJTDXKH
Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs VM = Midpoint Voltage (OVDD/2)
Input Data Valid
Output Data Valid
Figure 48. Boundary-Scan Timing Diagram
2.16
Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the MPC8535E. Note that the external cabled applications or long backplane applications (Gen1x & Gen2x) are not supported.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 78 Freescale Semiconductor
Serial ATA (SATA)
2.16.1
Requirements for SATA REF_CLK
Table 59. Reference Clock Input Requirements
Parameter Symbol tCLK_REF tCLK_TOL tCLK_RISE/tCLK_FALL tCLK_DUTY tCLK_CJ tCLK_PJ Min 100 -350 -- 45 -- -50 Typical -- 0 -- 50 -- -- Max 150 +350 1 55 100 +50 Unit MHz ppm ns % ps ps Notes 1 -- -- -- -- 2,3
The AC requirements for the SATA reference clock are listed in Table 59.
SD2_REF_CLK/_B reference clock cycle time SD2_REF_CLK/_B frequency tolerance SD_REF_CLK/_B rise/fall time (80%-20%) SD_REF_CLK/_B duty cycle (@50% X2VDD) SD_REF_CLK/_B cycle to cycle clock jitter (period jitter) SD_REF_CLK/_B phase jitter (peak-to-peak)
Note: 1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system. 2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter "Dj" should be less than or equal to 50 ps.
TH
Ref_CLK
TL
Figure 49. Reference Clock Timing Waveform
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 79
Serial ATA (SATA)
2.16.2
Differential Transmitter (TX) Output Characteristics
Table 60. Differential Transmitter (TX) Output Characteristics
Parameter Symbol tCH_SPEED Min -- Typical 1.5 3.0 666.4333 333.3333 250 Max -- Units Gbps -- TUI 666.4333 333.2167 200 670.2333 335.1167 450 ps Notes --
Table 60 provides the differential transmitter (TX) output characteristics for the SATA interface.
Channel Speed 1.5G 3.0G Unit Interval 1.5G 3.0G DC Coupled Common Mode Voltage TX Diff Output Voltage 1.5G 3.0G TX rise/fall time 1.5G 3.0G TX differential skew TX Differential pair impedance 1.5G TX Single ended impedance 1.5G TX AC common mode voltage (peak to peak) 1.5G 3.0G OOB Differential Delta OOB Common mode Delta TX Rise/Fall Imbalance TX Amplitude Imbalance TX Differential Mode Return loss 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz
Vdc_cm
mV
3 --
VSATA_TXDIFF
400 400 100 67 --
500 -- -- -- --
600 700 273 136 20
mV --
tSATA_20-80TX tSATA_TXSKEW ZSATA_TXDIFFIM
ps ps ohm -- --
85 ZSATA_TXSEIM 40
--
115 -- ohm
--
-- --
VSATA_TXCMMOD VSATA_OOBvdoff VSATA_OOBcm TSATA_TXR/Fbal TSATA_TXampbal
-- -- -- -- -- --
-- -- -- -- -- --
-- 50 25 50 20 10
mV mV mV % % 1 1 -- --
RLSATA_TXDD11
-- -- --
-- -- --
14 8 6 6 3 1
1, 2 dB
-- -- --
-- -- --
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 80 Freescale Semiconductor
Serial ATA (SATA)
Table 60. Differential Transmitter (TX) Output Characteristics (continued)
Parameter TX Common Mode Return loss 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz TX Impedance Balance 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz RLSATA_TXDC11 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz Deterministic jitter 1.5G 3.0G Total Jitter 1.5G 3.0G -- -- -- USATA_TXDJ -- -- -- -- -- 10 4 4 -- 0.18 0.14 0.42 0.32 UI -- USATA_TXTJ -- -- UI -- -- -- -- -- -- 30 20 10 Symbol Min Typical Max Units Notes
RLSATA_TXCC11
-- -- --
-- -- --
5 5 2
1, 2 dB
-- -- --
-- -- --
2 1 1
1, 2 dB
Notes: 1. Only applies when operating in 3.0Gb data rate mode. 2. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode. 3. Only applies to Gen1i mode.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 81
Serial ATA (SATA)
80% Differential data lines 20%
80%
20% tSATA_20-80TXfall TX+
tSATA_20-80TXrise
TX+
TXtSAT_TXSKEW LATE (TX+ is late)
TXtSAT_TXSKEW EARLY (TX+ is early)
Figure 50. Signal Rise and Fall Times and Differential Skew
2.16.3
Differential Receiver (RX) Input Characteristics
Table 61. Differential Receiver (RX) Input Characteristics
Parameter Symbol VSATA_RXDIFF 240 240 tSATA_20-80RX 100 67 -- -- 400 -- -- -- -- -- 600 750 273 136 -- 50 mVp-p -- ps -- tSATA_RXSKEW ps -- ZSATA_RXDIFFIM ZSATA_RXSEIM 40 Vdc_cm 200 -- 250 -- 5 450 mV 85 -- 115 ohm -- ohm Min Typical Max Units Notes 1
Table 61 provides the differential receiver (RX) input characteristics for the SATA interface.
RX Differential Input Voltage 1.5G 3.0G RX rise/fall time 1.5G 3.0G RX Differential skew 1.5G 3.0G RX Differential pair impedance 1.5G RX Single-Ended impedance 1.5G DC Coupled Common Mode Voltage
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 82 Freescale Semiconductor
Serial ATA (SATA)
Table 61. Differential Receiver (RX) Input Characteristics (continued)
Parameter RX Differential Mode Return loss 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz RX Common Mode Return loss 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz RX Impedance Balance 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz RLSATA_RXDC11 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz Deterministic jitter 1.5G 3.0G Total Jitter 1.5G 3.0G -- -- -- USATA_RXDJ -- -- -- -- -- 10 4 4 -- 0.4 0.47 0.65 0.65 UI -- USATA_RXTJ -- -- UI -- -- -- -- -- -- 30 30 20 Symbol Min Typical Max Units Notes 2, 3 -- -- -- -- -- -- 18 14 10
RLSATA_RXDD11
dB
-- -- --
-- -- --
8 3 1 2, 3, 4
RLSATA_RXCC11
-- -- --
-- -- --
5 5 2
dB
-- -- --
-- -- --
2 2 1 2, 3
dB
Notes: 1. The min values apply only to Gen1m, and Gen2m. the min values for Gen1i is 325 mVp-p and for Gen2i is 275 mVp-p. 2. Only applies when operating in 3.0Gb data rate mode. 3. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode. 4. The max value stated for 2.4 GHz - 3.0 GHz range only applies to Gen2i mode for Gen2m the value is 1. 5. Only applies to Gen1i mode.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 83
I2C
2.16.4
Out-of-Band (OOB) Electrical Characteristics
Table 62. Out-of-Band (OOB) Electrical Characteristics
Parameter Symbol Min Typical Max Units Notes -- VSATA_OOBDETE TSATA_UIOOB TSATA_UIOOBTXB 50 75 646.67 -- 100 125 666.67 160 200 200 686.67 -- mVp-p ps UI -- -- 480 -- UI -- -- 55 175 160 -- -- -- 175 525 UI ns ns -- -- -- --
Table 62 provides the Out-of-Band (OOB) electrical characteristics for the SATA interface of the MPC8535E.
OOB Signal Detection Threshold 1.5G 3.0G UI During OOB Signaling COMINIT/ COMRESET and COMWAKE Transmit Burst Length
COMINIT/ COMRESET Transmit Gap Length TSATA_UIOOBTXG
ap
COMWAKE Transmit Gap Length COMWAKE Gap Detection Windows COMINIT/ COMRESET Gap Detection Windows
TSATA_UIOOBTX
WakeGap
TSATA_OOBDet
WakeGap
TSATA_OOBDet
COMGap
2.17
I2C
I2C DC Electrical Characteristics
Table 63. I2C DC Electrical Characteristics
This section describes the DC and AC electrical characteristics for the I2C interfaces of the MPC8535E.
2.17.1
Table 63 provides the DC electrical characteristics for the I 2C interfaces.
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter Supply voltage 3.3 V Input high voltage level Input low voltage level Low level output voltage
Symbol OV DD VIH VIL VOL
Min 3.13 0.7 x OVDD -0.3 0
Max 3.47 OVDD + 0.3 0.3 x OVDD 0.2 x OVDD
Unit V V V V
Notes -- -- -- 1
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 84 Freescale Semiconductor
I2C
Table 63. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9 x OVDD(max) Capacitance for each I/O pin
Symbol tI2KHKL II CI
Min 0 -10 --
Max 50 10 10
Unit ns A pF
Notes 2 3 --
Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
2.17.2
I2C AC Electrical Specifications
Table 64. I2C AC Electrical Specifications
Table 64 provides the AC timing parameters for the I2C interfaces.
All values refer to VIH (min) and VIL (max) levels (see Table 63).
Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters I2C bus devices Data output delay time Set-up time for STOP condition Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals
Symbol 1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL
Min 0 1.3 0.6 0.6 0.6 100 -- 0
Max 400 -- -- -- -- -- -- -- 0.9 -- 300 300
Unit kHz s s s s ns s
Notes -- -- -- -- -- -- 2
tI2OVKL tI2PVKH tI2CR tI2CF
-- 0.6 -- --
-- s ns ns
3 -- 4 4
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 85
I2C
Table 64. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 63).
Parameter Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis)
Symbol 1 tI2KHDX VNL VNH
Min 1.3 0.1 x OV DD 0.2 x OV DD
Max -- -- --
Unit s V V
Notes -- -- --
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. As a transmitter, the MPC8535E provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When the MPC8535E acts as the I2C bus master while transmitting, the MPC8535E drives both SCL and SDA. As long as the load on SCL and SDA are balanced, the MPC8535E would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the MPC8535E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal 16): I2C Source Clock Frequency 333 MHz 266 MHz 200 MHz 133 MHz FDR Bit Setting 0x2A 0x05 0x26 0x00 Actual FDR Divider Selected 896 704 512 384 378 KHz 390 KHz 346 KHz Actual I2C SCL Frequency Generated 371 KHz 2C frequency calculation, refer to Determining the I2C Frequency Divider Ratio for SCL (AN2919). Note that For details of the I the I2C Source Clock Frequency is half of the CCB clock frequency for the MPC8535E. 3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF.
Figure 51 provides the AC test load for the I2C.
Output Z0 = 50 OVDD/2
RL = 50
Figure 51. I2C AC Test Load
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 86 Freescale Semiconductor
GPIO
Figure 52 shows the AC timing diagram for the I2C bus.
SDA tI2CF tI2CL SCL tI2SXKL S tI2CH tI2DXKL, tI2OVKL tI2SVKH Sr tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF
Figure 52. I2C Bus AC Timing Diagram
2.18
GPIO
This section describes the DC and AC electrical specifications for the GPIO interface of the MPC8535E.
2.18.1
GPIO DC Electrical Characteristics
Table 65. GPIO DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = -2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA) Symbol VIH VIL IIN VOH VOL Min 2 - 0.3 -- 2.4 -- Max OVDD + 0.3 0.8 5 -- 0.4 Unit V V A V V
Table 65 provides the DC electrical characteristics for the GPIO interface.
Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
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PCI
2.18.2
GPIO AC Electrical Specifications
Table 66. GPIO Input and Output AC Timing Specifications1
Characteristic Symbol 2 tPIWID tGTOWID Min 7.5 12 Unit ns ns Notes 3 --
Table 66 provides the GPIO input and output AC timing specifications.
GPIO inputs--minimum pulse width GPIO outputs--minimum pulse width
Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation. 3. The minimum pulse width is a function of the MPX/Platform clock. The minimum pulse width must be greater than or equal to 4 times the MPX/Platform clock period.
Figure 53 provides the AC test load for the GPIO.
Output Z0 = 50 OVDD/2
RL = 50
Figure 53. GPIO AC Test Load
2.19
PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8535E.
2.19.1
PCI DC Electrical Characteristics
Table 67. PCI DC Electrical Characteristics 1
Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- 2.4 -- Max OVDD + 0.3 0.8 5 -- 0.4 Unit V V A V V
Table 67 provides the DC electrical characteristics for the PCI interface.
High-level input voltage Low-level input voltage Input current (VIN 2 = 0 V or VIN = V DD) High-level output voltage (OVDD = min, IOH = -2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA)
Notes: 1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications. 2. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
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PCI
2.19.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input clock. Table 68 provides the PCI AC timing specifications at 66 MHz. Table 68. PCI AC Timing Specifications at 66 MHz
Parameter SYSCLK to output valid Output hold from SYSCLK SYSCLK to output high impedance Input setup to SYSCLK Input hold from SYSCLK REQ64 to HRESET
9 setup
Symbol 1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH
Min -- 2.0 -- 3.0 0 10 x tSYS 0 10 0.6 0.6
Max 6.0 -- 14 -- -- -- 50 -- 2.1 2.1
Unit ns ns ns ns ns clocks ns clocks ns ns
Notes 2, 3 2 2, 4 2, 5 2, 5 6, 7 7 8 -- --
time
tPCRVRH tPCRHRX tPCRHFV tPCICLK tPCICLK
HRESET to REQ64 hold time HRESET high to first FRAME assertion Rise time (20%-80%) Failing time (20%-80%)
Notes: 1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 x OVDD of the signal in question for 3.3-V PCI signaling levels. 4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. Input timings are measured at the pin. 6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values see Section 22, "Clocking." 7. The setup and hold time is with respect to the rising edge of HRESET. 8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus Specifications. 9. The reset assertion timing requirement for HRESET is 100 s.
Figure 54 provides the AC test load for PCI.
Output Z0 = 50 OVDD/2
RL = 50
Figure 54. PCI AC Test Load
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 89
High-Speed Serial Interfaces
Figure 55 shows the PCI input AC timing conditions.
CLK tPCIVKH tPCIXKH Input
Figure 55. PCI Input AC Timing Measurement Conditions Figure 56 shows the PCI output AC timing conditions.
CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output
Figure 56. PCI Output AC Timing Measurement Condition
2.20
High-Speed Serial Interfaces
The MPC8535E features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for SGMII or SATA. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes Reference Clocks. The SerDes data lane's transmitter and receiver reference circuits are also shown.
2.20.1 Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 57 shows how the signals are defined. For illustration purposes, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B. Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-Ended Swing The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a peak-to-peak swing of A - B Volts. This is also referred as each signal wire's Single-Ended Swing. 2. Differential Output Voltage, VOD (or Differential Output Swing): The Differential Output Voltage (or Swing) of the transmitter, V OD, is defined as the difference of the two complimentary output voltages: VSDn_TX - VSDn_TX. The VOD value can be either positive or negative. 3. Differential Input Voltage, VID (or Differential Input Swing):
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High-Speed Serial Interfaces
The Differential Input Voltage (or Swing) of the receiver, V ID, is defined as the difference of the two complimentary input voltages: VSDn_RX - V SDn_RX. The VID value can be either positive or negative. 4. Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak Voltage, VDIFFp = |A - B| Volts. 5. Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak-to-Peak Voltage, VDIFFp-p = 2*VDIFFp = 2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as V TX-DIFFp-p = 2*|VOD|. 6. Common Mode Voltage, Vcm The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = VSDn_TX + VSDn_TX = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component's output to the other's input. Sometimes, it may be even different between the receiver input and driver output circuits within the same component. It is also referred as the DC offset in some occasion.
SDn_TX or SDn_RX A Volts
Vcm = (A + B) / 2 SDn_TX or SDn_RX B Volts
Differential Swing, VID or VOD = A - B Differential Peak Voltage, VDIFFp = |A - B| Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Figure 57. Differential Voltage Definitions for Transmitter or Receiver To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output's differential swing (VOD) has the same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV, in other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (V DIFFp-p) is 1000 mV p-p.
2.20.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks for PCI Express are SD1_REF_CLK and, SD1_REF_CLK. The SerDes reference clocks for the SATA and SGMII interfaces are SD2_REF_CLK and, SD2_REF_CLK.
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High-Speed Serial Interfaces
The following sections describe the SerDes reference clock requirements and some application information.
2.20.2.1
* *
SerDes Reference Clock Receiver Characteristics
Figure 58 shows a receiver reference diagram of the SerDes reference clocks. The supply voltage requirements for X2VDD are specified in Table 2 and Table 3. SerDes Reference Clock Receiver Reference Circuit Structure -- The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 58. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50- termination to SGND (xcorevss) followed by on-chip AC-coupling. -- The external reference clock driver must be able to drive this termination. -- The SerDes reference clock input can be either differential or single-ended. See the Differential Mode and Single-ended Mode description below for further detailed requirements. The maximum average current requirement that also determines the common mode voltage range -- When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. -- This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1V above SnGND (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA (0-0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800mV with the common mode voltage at 400mV. -- If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 to SnGND (xcorevss) DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. The input amplitude requirement -- This requirement is described in detail in the following sections.
*
*
50 SDn_REF_CLK Input Amp SDn_REF_CLK 50
Figure 58. Receiver of SerDes Reference Clocks
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High-Speed Serial Interfaces
2.20.2.2 DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8535E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. * Differential Mode -- The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external DC-coupled or AC-coupled connection. -- For external DC-coupled connection, as described in section 2.20.2.1, the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV. Figure 59 shows the SerDes reference clock input requirement for DC-coupled connection scheme. -- For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SnGND. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (SnGND). Figure 60 shows the SerDes reference clock input requirement for AC-coupled connection scheme. Single-ended Mode -- The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to ground. -- The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 61 shows the SerDes reference clock input requirement for single-ended signaling mode. -- To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
*
SDn_REF_CLK
200 mV < Input Amplitude or Differential Peak < 800 mV Vmax < 800 mV
100 mV < Vcm < 400 mV
SDn_REF_CLK
Vmin > 0 V
Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled)
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High-Speed Serial Interfaces
200mV < Input Amplitude or Differential Peak < 800 mV SDn_REF_CLK Vmax < Vcm + 400 mV
Vcm
SDn_REF_CLK
Vmin > Vcm - 400 mV
Figure 60. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
SDn_REF_CLK
0V SDn_REF_CLK
Figure 61. Single-Ended Reference Clock Input DC Requirements
2.20.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to SnGND (xcorevss), the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection. LVPECL (Low Voltage Positive Emitter-Coupled Logic) outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 62 to Figure 65 below are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8535E SerDes reference clock receiver requirement provided in this document.
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High-Speed Serial Interfaces
Figure 62 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8535E SerDes reference clock input's DC requirement.
HCSL CLK Driver Chip
CLK_Out 33 SDn_REF_CLK 50
Clock Driver 33 CLK_Out
100 differential PWB trace
SerDes Refer. CLK Receiver
SDn_REF_CLK
50
Total 50 . Assume clock driver's output impedance is about 16 .
Clock driver vendor dependent source termination resistor
Figure 62. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only) Figure 63 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver's common mode voltage is higher than the MPC8535E SerDes reference clock input's allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50- termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component.
LVDS CLK Driver Chip
CLK_Out 10 nF SDn_REF_CLK 50
MPC8535E
Clock Driver
100 differential PWB trace
SerDes Refer. CLK Receiver
CLK_Out
10 nF
SDn_REF_CLK
50
Figure 63. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
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High-Speed Serial Interfaces
Figure 64 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver's DC levels (both common mode voltages and output swing) are incompatible with MPC8535E SerDes reference clock input's DC requirement, AC-coupling has to be used. Figure 64 assumes that the LVPECL clock driver's output impedance is 50. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 depending on clock driver vendor's requirement. R2 is used together with the SerDes reference clock receiver's 50- termination resistor to attenuate the LVPECL output's differential peak level such that it meets the MPC8535E SerDes reference clock's differential input amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output's differential peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip.
LVPECL CLK Driver Chip
CLK_Out R2 10nF SDn_REF_CLK
MPC8535E 50
Clock Driver
R1
100 differential PWB trace R2 10 nF SDn_REF_CLK
SerDes Refer. CLK Receiver
CLK_Out R1
50
Figure 64. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 65 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8535E SerDes reference clock input's DC requirement. Single-Ended CLK Driver Chip
Total 50 . Assume clock driver's output impedance is about 16 . 33 CLK_Out SDn_REF_CLK 50
Clock Driver
100 differential PWB trace
SerDes Refer. CLK Receiver
50
SDn_REF_CLK
50
Figure 65. Single-Ended Connection (Reference Only)
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High-Speed Serial Interfaces
2.20.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 ohms to match the transmission line and reduce reflections which are a source of noise to the system. Table 69 describes some AC parameters common to SGMII and PCI Express protocols. Table 69. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.0V 5%.
Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage Rising edge rate (SDn_REF_CLK) to falling edge rate (SDn_REF_CLK) matching
Symbol Rise Edge Rate Fall Edge Rate VIH VIL Rise-Fall Matching
Min 1.0 1.0 +200 -- --
Max 4.0 4.0 -- -200 20
Unit V/ns V/ns mV mV %
Notes 2, 3 2, 3 2 2 1, 4
Notes: 1. Measurement taken from single ended waveform. 2. Measurement taken from differential waveform. 3. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 66. 4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 67.
VIH
=
+200 0.0 V
VIL = -200 mV SDn_REF_CL K minus
Figure 66. Differential Measurement Points for Rise and Fall Time
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High-Speed Serial Interfaces
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
Figure 67. Single-Ended Measurement Points for Rise and Fall Time Matching The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application usage. See the following sections for detailed information: * * Section 2.9.3.2, "AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK" Section 2.21.2, "AC Requirements for PCI Express SerDes Clocks"
2.20.2.4.1 Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30-33 kHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used. SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source.
2.20.3 SerDes Transmitter and Receiver Reference Circuits
Figure 68 shows the reference circuits for SerDes data lane's transmitter and receiver.
SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50 50 SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50
50 Transmitter
Receiver
Figure 68. SerDes Transmitter and Receiver Reference Circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, SATA or SGMII) in this document based on the application usage: * * * Section 2.9.3, "SGMII Interface Electrical Characteristics" Section 2.21, "PCI Express" Section 2.16, "Serial ATA (SATA)"
Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 98 Freescale Semiconductor
PCI Express
2.21
PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8535E.
2.21.1
DC Requirements for PCI Express SD1_REF_CLK and SD1_REF_CLK
For more information, see Section 2.20.2, "SerDes Reference Clocks."
2.21.2
AC Requirements for PCI Express SerDes Clocks
Table 70. SD1_REF_CLK and SD1_REF_CLK AC Requirements
Table 70 lists AC requirements.
Symbol tREF tREFCJ tREFPJ REFCLK cycle time
Parameter Description
Min -- -- -50
Typical 10 -- --
Max -- 100 50
Units ns ps ps
Notes 1 -- 1,2,3
REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles Phase jitter. Deviation in edge location with respect to mean edge location
Notes: 1. Tj at BER of 10E-6 86 ps Max. 2. Total peak-to-peak deterministic jitter "Dj" should be less than or equal to 42 ps. 3. Limits from "PCI Express CEM Rev 2.0" and measured per "PCI Express Rj, D, and Bit Error Rates".
2.21.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million 15 (ppm) of each other at all times. This is specified to allow bit rate clock sources with a +/- 300 ppm tolerance.
2.21.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer, please use the PCI Express Base Specification. REV. 1.0a document.
2.21.4.1
Differential Transmitter (TX) Output
Table 71 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 71. Differential Transmitter (TX) Output Specifications
Symbol UI Parameter Unit Interval Min 399.88 Nom 400 Max 400.12 Units ps Comments Each UI is 400 ps 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. VTX-DIFFp-p = 2*|VTX-D+ - VTX-D-| See Note 2.
VTX-DIFFp-p
Differential Peak-to-Peak Output Voltage
0.8
--
1.2
V
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 99
PCI Express
Table 71. Differential Transmitter (TX) Output Specifications (continued)
Symbol VTX-DE-RATIO Parameter De- Emphasized Differential Output Voltage (Ratio) Minimum TX Eye Width Maximum time between the jitter median and maximum deviation from the median. D+/D- TX Output Rise/Fall Time RMS AC Peak Common Mode Output Voltage Absolute Delta of DC Common Mode Voltage During L0 and Electrical Idle Min -3.0 Nom -3.5 Max -4.0 Units dB Comments Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the V TX-DIFFp-p of the first bit after a transition. See Note 2. The maximum Transmitter jitter can be derived as TTX-MAX-JITTER = 1 - TTX-EYE= 0.3 UI. See Notes 2 and 3. Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2 and 3. See Notes 2 and 5 VTX-CM-ACp = RMS(|VTXD+ +VTXD-|/2 - V TX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ +VTX-D-|/2 See Note 2 |VTX-CM-DC (during L0) - VTX-CM-Idle-DC (During Electrical Idle) |<=100 mV VTX-CM-DC = DC(avg) of |VTX-D+ +VTX-D-|/2 [L0] VTX-CM-Idle-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 [Electrical Idle] See Note 2. |VTX-CM-DC-D+ - VTX-CM-DC-D-| <= 25 mV VTX-CM-DC-D+ = DC(avg) of |V TX-D+| VTX-CM-DC-D- = DC (avg) of |VTX-D-| See Note 2. VTX-IDLE-DIFFp = |VTX-IDLE-D+ -VTX-IDLE-D-| <= 20 mV See Note 2. The total amount of voltage change that a transmitter can apply to sense whether a low impedance Receiver is present. See Note 6. The allowed DC Common Mode voltage under any conditions. See Note 6. The total current the Transmitter can provide when shorted to its ground Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set
TTX-EYE
0.70
--
--
UI
TTX-EYE-MEDIAN-toMAX-JITTER
--
--
0.15
UI
TTX-RISE, TTX-FALL VTX-CM-ACp
0.125 --
-- --
-- 20
UI mV
VTX-CM-DC-ACTIVEIDLE-DELTA
0
--
100
mV
VTX-CM-DC-LINE-DELTA Absolute Delta of DC Common Mode between D+ and D- VTX-IDLE-DIFFp Electrical Idle differential Peak Output Voltage The amount of voltage change allowed during Receiver Detection The TX DC Common Mode Voltage TX Short Circuit Current Limit Minimum time spent in Electrical Idle
0
--
25
mV
0
--
20
mV
VTX-RCV-DETECT
--
--
600
mV
VTX-DC-CM
0
--
3.6
V
ITX-SHORT TTX-IDLE-MIN
-- 50
-- --
90 --
mA UI
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 100 Freescale Semiconductor
Table 71. Differential Transmitter (TX) Output Specifications (continued)
Symbol TTX-IDLE-SET-TO-IDLE Parameter Maximum time to transition to a valid electrical idle after sending an electrical Idle ordered set Min -- Nom -- Max 20 Units UI Comments After sending an Electrical Idle ordered set, the Transmitter must meet all Electrical Idle Specifications within this time. This is considered a debounce time for the Transmitter to meet Electrical Idle after transitioning from L0. Maximum time to meet all TX specifications when transitioning from Electrical Idle to sending differential data. This is considered a debounce time for the TX to meet all TX specifications after leaving Electrical Idle
TTX-IDLE-TO-DIFF-DATA Maximum time to transition to valid TX specifications after leaving an electrical idle condition RLTX-DIFF RLTX-CM ZTX-DIFF-DC ZTX-DC LTX-SKEW CTX Differential Return Loss Common Mode Return Loss DC Differential TX Impedance Transmitter DC Impedance Lane-to-Lane Output Skew AC Coupling Capacitor Crosslink Random Timeout
--
--
20
UI
12 6 80 40 -- 75
-- -- 100 -- -- --
-- -- 120 -- 500 + 2 UI 200
dB dB ps nF
Measured over 50 MHz to 1.25 GHz. See Note 4 Measured over 50 MHz to 1.25 GHz. See Note 4 TX DC Differential mode Low Impedance Required TX D+ as well as D- DC Impedance during all states Static skew between any two Transmitter Lanes within a single Link All Transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 8. This random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one Downstream and one Upstream Port. See Note 7.
Tcrosslink
0
--
1
ms
Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 52 and measured over any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 50) 3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 ohms to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes--see Figure 52). Note that the series capacitors CTX is optional for the return loss measurement. 5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 52 for both VTX-D+ and V TX-D-. 6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a 7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a 8. SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.
PCI Express
2.21.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 69 is specified using the passive compliance/test measurement load (see Figure 71) in place of any real PCI Express interconnect + RX component. There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. NOTE It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits).
Figure 69. Minimum Transmitter Timing and Voltage Output Compliance Specifications
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 102 Freescale Semiconductor
2.21.4.3
Differential Receiver (RX) Input Specifications
Table 72 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins. Table 72. Differential Receiver (RX) Input Specifications
Symbol UI Parameter Unit Interval Min 399.8 8 0.175 Nom 400 Max 400.12 Units ps Comments Each UI is 400 ps 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-| See Note 2. The maximum interconnect media and Transmitter jitter that can be tolerated by the Receiver can be derived as TRX-MAX-JITTER = 1 - TRX-EYE= 0.6 UI. See Notes 2 and 3. Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2, 3 and 7. VRX-CM-ACp = |VRXD+ - VRXD-|/2 +VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ +V RX-D-|/2 See Note 2 Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at +300 mV and -300 mV, respectively. See Note 4 Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at 0 V. See Note 4 RX DC Differential mode impedance. See Note 5 Required RX D+ as well as D- DC Impedance (50 20% tolerance). See Notes 2 and 5. Required RX D+ as well as D- DC Impedance when the Receiver terminations do not have power. See Note 6. VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ -VRX-D-| Measured at the package pins of the Receiver An unexpected Electrical Idle (V RX-DIFFp-p < VRX-IDLE-DET-DIFFp-p) must be recognized no longer than TRX-IDLE-DET-DIFF-ENTERING to signal an unexpected idle condition.
VRX-DIFFp-p
Differential Peak-to-Peak Output Voltage Minimum Receiver Eye Width
--
1.200
V
TRX-EYE
0.4
--
--
UI
TRX-EYE-MEDIAN-to-MAX Maximum time between the jitter -JITTER median and maximum deviation from the median.
--
--
0.3
UI
VRX-CM-ACp
AC Peak Common Mode Input Voltage Differential Return Loss
--
--
150
mV
RLRX-DIFF
15
--
--
dB
RLRX-CM ZRX-DIFF-DC ZRX-DC ZRX-HIGH-IMP-DC
Common Mode Return Loss DC Differential Input Impedance DC Input Impedance Powered Down DC Input Impedance Electrical Idle Detect Threshold Unexpected Electrical Idle Enter Detect Threshold Integration Time
6 80 40 200 k
-- 100 50 --
-- 120 60 --
dB
VRX-IDLE-DET-DIFFp-p TRX-IDLE-DET-DIFFENTERTIME
65 --
-- --
175 10
mV ms
PCI Express
Table 72. Differential Receiver (RX) Input Specifications (continued)
Symbol LTX-SKEW Parameter Total Skew Min -- Nom -- Max 20 Units ns Comments Skew across all lanes on a Link. This includes variation in the length of SKP ordered set (for example, COM and one to five Symbols) at the RX as well as any delay differences arising from the interconnect itself.
Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 71 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 70). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to 300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes - see Figure 71). Note: that the series capacitors CTX is optional for the return loss measurement. 5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM) there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port. 6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be measured at 300 mV above the RX ground. 7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.
2.22
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 70 is specified using the passive compliance/test measurement load (see Figure 71) in place of any real PCI Express RX component. Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement load (see Figure 71) will be larger than the minimum Receiver eye diagram measured over a range of systems at the input Receiver of any real PCI Express component. The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input Receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in Figure 70) expected at the input Receiver based on some adequate combination of system simulations and the Return Loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 104 Freescale Semiconductor
Clocking
NOTE The reference impedance for return loss measurements is 50. to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50. probes--see Figure 71). Note that the series capacitors, CTX, are optional for the return loss measurement.
Figure 70. Minimum Receiver Eye Timing and Voltage Compliance Specification
2.22.0.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 71. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary.
Figure 71. Compliance Test/Measurement Load
2.23
Clocking
This section describes the PLL configuration of the MPC8535E. Note that the platform clock is identical to the core complex bus (CCB) clock.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 105
Clocking
2.23.1
Clock Ranges
Table 73 provides the clocking specifications for the processor cores and Table 74 provides the clocking specifications for the memory bus. Table 73. Processor Core Clocking Specifications
Maximum Processor Core Frequency Characteristic 600 MHz Min e500 core processor frequency CCB frequency DDR Data Rate 600 400 400 Max 600 400 400 800 MHz Min 600 400 400 Max 800 400 400 1000 MHz Min 600 333 400 Max 1000 400 400 1250 MHz Min 600 333 400 Max 1250 500 500 MHz 1, 2 Unit Notes
Notes: 1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. See Section 2.23.2, "CCB/SYSCLK PLL Ratio," Section 2.23.3, "e500 Core PLL Ratio,"and Section 2.23.4, "DDR/DDRCLK PLL Ratio," for ratio settings. 2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically possible via valid clock ratio setting in some condition, is not supported.
The DDR memory controller can run in either synchronous or asynchronous mode. When running in synchronous mode, the memory bus is clocked relative to the platform clock frequency. When running in asynchronous mode, the memory bus is clocked with its own dedicated PLL. Table 74 provides the clocking specifications for the memory bus. Table 74. Memory Bus Clocking Specifications
Maximum Processor Core Frequency Characteristic Min DDR Memory bus clock speed 200 600, 800, 1000, 1250 Max 250 MHz 1, 2, 3, 4 Unit Notes
Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies. See Section 2.23.2, "CCB/SYSCLK PLL Ratio," Section 2.23.3, "e500 Core PLL Ratio," and Section 2.23.4, "DDR/DDRCLK PLL Ratio," for ratio settings. 2. The Memory bus clock refers to the MPC8535E memory controllers' MCK[0:5] and MCK[0:5] output clocks, running at half of the DDR data rate. 3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency, asynchronous mode must be used. 4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See Section 2.23.4, "DDR/DDRCLK PLL Ratio." The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR data rate.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 106 Freescale Semiconductor
Clocking
2.23.2
CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency of the CCB is set using the following reset signals, as shown in Table 75: * * SYSCLK input signal Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Table 75. CCB Clock Ratio
Binary Value of LA[28:31] Signals 0000 0001 0010 0011 0100 0101 0110 0111 CCB:SYSCLK Ratio Reserved Reserved Reserved 3:1 4:1 5:1 6:1 Reserved Binary Value of LA[28:31] Signals 1000 1001 1010 1011 1100 1101 1110 1111 CCB:SYSCLK Ratio 8:1 9:1 10:1 Reserved 12:1 Reserved Reserved Reserved
2.23.3
e500 Core PLL Ratio
Table 76 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined by the binary value of LBCTL, LALE and LGPL2 at power up, as shown in Table 76. Table 76. e500 Core to CCB Clock Ratio
Binary Value of LBCTL, LALE, LGPL2 Signals 000 001 010 011 e500 core: CCB Clock Ratio 4:1 9:2 Reserved 3:2 Binary Value of LBCTL, LALE, LGPL2 Signals 100 101 110 111 e500 core: CCB Clock Ratio 2:1 5:2 3:1 7:2
2.23.4
DDR/DDRCLK PLL Ratio
The DDR memory controller complex can be synchronous with, or asynchronous to, the CCB, depending on configuration. Table 77 describes the clock ratio between the DDR memory controller complex and the DDR/DDRCLK PLL reference clock, DDRCLK, which is not the memory bus clock. When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default mode of operation is for the DDR data rate for the DDR controller to be equal to the CCB clock rate in synchronous mode, or the resulting DDR PLL rate in asynchronous mode. In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 77 reflects the DDR data rate to DDRCLK ratio, since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 107
Clocking
Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode. The DDRCLKDR configuration register in the Global Utilities block allows the DDR controller to be run in a divided down mode where the DDR bus clock is half the speed of the default configuration. Changing of these defaults must be completed prior to initialization of the DDR controller. Table 77. DDR Clock Ratio
Functional Signals Reset Configuration Name Value (Binary) 000 001 010 TSEC_1588_TRIG_OUT[0:1], TSEC1_1588_CLK_OUT 011 cfg_ddr_pll[0:2] 100 101 110 111 10:1 12:1 Reserved Synchronous mode DDR:DDRCLK Ratio 3:1 4:1 6:1 8:1
2.23.5
PCI Clocks
The integrated PCI controller in MPC8535E supports PCI input clock frequency in the range of 33-66 MHz. The PCI input clock can be applied from SYSCLK in synchronous mode or PCI1_CLK in asynchronous mode. For specifications on the PCI1_CLK, refer to the PCI 2.2 Specification. The use of PCI1_CLK is optional if SYSCLK is in the range of 33-66 MHz. If SYSCLK is outside this range then use of PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 108 Freescale Semiconductor
Thermal
2.23.6
2.23.6.1
Frequency Options
SYSCLK to Platform Frequency Options
Table 78 shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in comparison to the memory bus clock speed. Table 78. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
CCB to SYSCLK Ratio 33.33 41.66 66.66 SYSCLK (MHz) 83 100 111 133.33
Platform /CCB Frequency (MHz) 3 4 5 6 8 10 12 333 400 333 417 500 333 400 333 415 500 400 500 333 444 400
2.24
Thermal
This section describes the thermal specifications of the MPC8535E.
2.24.1
Thermal Characteristics
Table 79. Package Thermal Characteristics
Characteristic JEDEC Board Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Symbol RJA RJA RJA Value 23 18 18 Unit C/W C/W C/W Notes 1, 2 1, 2 1, 2
Table 79 provides the package thermal characteristics.
Junction-to-ambient Natural Convection Junction-to-ambient Natural Convection Junction-to-ambient (@200 ft/min)
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 109
Thermal
Table 79. Package Thermal Characteristics (continued)
Characteristic Junction-to-ambient (@200 ft/min) Junction-to-board thermal Junction-to-case thermal JEDEC Board Four layer board (2s2p) -- -- Symbol RJA RJB R JC Value 14 10 < 0.1 Unit C/W C/W C/W Notes 1, 2 3 4
Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal. 3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 *C/W C/W
Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.For system thermal modeling, the MPC8535E thermal model without a lid is shown in Figure 72 The substrate is modeled as a block 29 x 29 x 1.2 mm with an in-plane conductivity of 19.8 W/m*K and a through-plane conductivity of 1.13 W/m*K. The solder balls and air are modeled as a single block 29 x 29 x 0.5 mm with an in-plane conductivity of 0.034 W/m*K and a through plane conductivity of 12.1 W/m*K. The die is modeled as 9.6 x 9.57 mm with a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed thermal resistance between the die and substrate assuming a conductivity of 7.5 W/m*K in the thickness dimension of 0.07 mm. The die is centered on the substrate. The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual dimensions.
2.24.2
Recommended Thermal Model
Table 80. MPC8535E Thermal Model
Conductivity Value Die (9.6x9.6 x 0.85 mm) Silicon Temperature dependent -- Units
Bump/Underfill (9.6 x 9.6 x 0.07 mm) Collapsed Thermal Resistance Kz 7.5 Substrate (29 x 29 x 1.2 mm) Kx Ky Kz 19.8 19.8 1.13 Solder and Air (29 x 29 x 0.5 mm) Kx Ky Kz 0.034 0.034 12.1 W/m*K W/m*K W/m*K
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 110 Freescale Semiconductor
Thermal
Bump/underfill
Die Substrate
Section A-A
Solder/air
A
A
Top View
Figure 72. System Level Thermal Model for MPC8535E (Not to Scale) The Flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer for flow over the part in standard JEDEC environments, as well as the heat spreading in the board under the package. In a real system, however, the part will require a heat sink to be mounted on it. In this case, the predominant heat flow path will be from the die to the heat sink. Grid density lower than currently in the package library file will suffice for these simulations. The user will need to determine the optimal grid for their specific case.
2.24.3
Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design--the heat sink, airflow, and thermal interface material.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 111
Thermal
The recommended attachment method to the heat sink is illustrated in Figure 73. The heat sink should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45 Newton).
FC-PBGA Package Heat Sink Heat Sink Clip
Thermal Interface Material
Die
Printed-Circuit Board
Figure 73. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the device. Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that will allow the MPC8535E to function in various environments.
2.24.3.1
Internal Package Conduction Resistance
For the packaging technology, shown in Table 70, the intrinsic internal conduction thermal resistance paths are as follows: * The die junction-to-case thermal resistance * The die junction-to-board thermal resistance Figure 74 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Solder Spheres
Printed-Circuit Board
External Resistance
Radiation
Convection
(Note the internal versus external package resistance)
Figure 74. Package with Heat Sink Mounted to a Printed-Circuit Board
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 112 Freescale Semiconductor
System Clocking
The heat sink removes most of the heat from the device for most applications. Heat generated on the active side of the chip is conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.
2.24.3.2
Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The performance of thermal interface materials improves with increased contact pressure. This performance characteristic chart is generally provided by the thermal interface vendors.
3
3.1
Hardware Design Considerations
System Clocking
This section provides electrical and thermal design recommendations for successful application of the MPC8535E.
This device includes seven PLLs: * The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Section 2.23.2, "CCB/SYSCLK PLL Ratio." * The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500 core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 2.23.3, "e500 Core PLL Ratio/" * The PCI PLL generates the clocking for the PCI bus * The local bus PLL generates the clock for the local bus. * There is a PLL for the SerDes1 block to be used for PCI Express interface * There is a PLL for the SerDes2 block to be used for SGMII and SATA interfaces. * The DDR PLL generates the DDR clock from the externally supplied DDRCLK input in asynchronous mode. The frequency ratio between the DDR clock and DDRCLK is described in Section 2.23.4, "DDR/DDRCLK PLL Ratio."
3.2
3.2.1
Power Supply Design and Sequencing
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE, AVDD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits per PLL power supply as illustrated in Figure 75, one to each of the AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of 783 FC-PBGA the footprint, without the inductance of vias.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 113
Pin States in Deep Sleep State
Figure 75 shows the PLL power supply filter Circuit.
10 V DD 2.2 F 2.2 F Low ESL Surface Mount Capacitors AVDD
GND
Figure 75. MPC8535E PLL Power Supply Filter Circuit
The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 76. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-F capacitor is closest to the balls, followed by the 1-F capacitor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and direct.
1.0 AVDD - SRDS 2.2 F
1
SnVDD
2.2 F
1
0.003 F
GND
1. An 0805 sized capacitor is recommended for system initial bring-up
Figure 76. SerDes PLL Power Supply Filter Circuit
Note the following: * AVDD should be a filtered version of SVDD. * Signals on the SerDes interface are fed from the XVDD power plane.
3.3
Pin States in Deep Sleep State
In all low power mode by default, all input and output pads remain driven as per normal functional operation. The inputs remain enabled. The exception is that in Deep Sleep mode, GCR[DEEPSLEEP_Z] can be used to tristate a subset of output pads, and disable the receivers of input pads as defined in Table 1. See the MPC8536E PowerQUICCTM III Integrated Processor Reference Manual for details.
3.4
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8535E system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD pin of the device. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD, OVDD, GVDD, and LVDD, and GND power planes in the PCB, utilizing short low impedance traces to minimize inductance. Capacitors must be placed directly under the device using a standard escape pattern as much as possible. If some caps are to be placed surrounding the part it should be routed with short and large trace to minimize the inductance.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 114 Freescale Semiconductor
SerDes Block Power Supply Decoupling Recommendations
These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, TVDD, BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors--100-330 F (AVX TPS tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values types and quantity of bulk capacitors.
3.5
SerDes Block Power Supply Decoupling Recommendations
he SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SnVDD and XnVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. * First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. Second, there should be a 1-F ceramic chip capacitor from each SerDes supply (SnVDD and XnVDD) to the board ground plane on each side of the device. This should be done for all SerDes supplies. Third, between the device and any SerDes voltage regulator there should be a 10-F, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
* *
3.6
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to VDD,TVDD, BVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD,TVDD, BVDD, OVDD, GVDD, and LVDD and GND pins of the device.
3.7
Pull-Up and Pull-Down Resistor Requirements
The MPC8535E requires weak pull-up resistors (2-10 k is recommended) on open drain type pins including I2C pins and MPIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. The following pins must NOT be pulled down during power-on reset: TSEC1_TXD[3], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Please refer to the pinlist table (see Table 62) of the individual device for more details. See the PCI 2.2 specification for all pull-ups required for PCI.
3.8
Output Buffer DC Impedance
The MPC8535E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C).
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 115
Configuration Pin Muxing
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 77). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
OV DD
RN
SW2 Data Pad SW1
RP
OGND
Figure 77. Driver Impedance Measurement
Table 81 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD, 105C.
Table 81. Impedance Characteristics
Impedance RN RP Local Bus, Ethernet, DUART, Control, Configuration, Power Management 45 Target 45 Target PCI 45 Target (cfg_pci_impd=1) 25 Target (cfg_pci_impd=0) 45 Target (cfg_pci_impd=1) 25 Target (cfg_pci_impd=0) DDR DRAM 18 Target (full strength mode) 36 Target (full strength mode) 18 Target (full strength mode) 36 Target (full strength mode) Symbol Unit Z0 Z0

Note: Nominal supply voltages. See Table 1.
3.9
Configuration Pin Muxing
The MPC8535E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k. This value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 116 Freescale Semiconductor
JTAG Configuration Signals
level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.
3.10
JTAG Configuration Signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredicatable results. Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST to be asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation. While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP), which implements the debug interface to the chip. The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 78 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The COP interface has a standard header, shown in Figure 79, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 79 is common to all known emulators.
3.10.1
Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections: * TRST should be tied to HRESET through a 0 k isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 78. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. * No pull-up/pull-down is required for TDI, TMS, or TDO.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 117
JTAG Configuration Signals OV DD SRESET HRESET 10 k SRESET 6 HRESET1
From Target Board Sources (if any)
10 k
13 11
COP_HRESET COP_SRESET 10 k 10 k
5
10 k 10 k TRST1
1 3 5 7 9 11
2 4 6 8 10 12
4 6 53 COP Header 15 14 3
COP_TRST COP_VDD_SENSE2 NC COP_CHKSTP_OUT 10 k 10 k COP_CHKSTP_IN 10
CKSTP_OUT
KEY 13 No pin
8 COP_TMS 9 COP_TDO COP_TDI COP_TCK 7 2 10 12 16 NC NC
4
CKSTP_IN TMS TDO TDI TCK 10 k
15
16
COP Connector Physical Pinout
1 3
Notes: 1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 10 resistor for short-circuit/current-limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 78. JTAG Interface Connection
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 118 Freescale Semiconductor
Guidelines for High-Speed Interface Termination
COP_TDO COP_TDI NC COP_TCK COP_TMS COP_SRESET COP_HRESET COP_CHKSTP_OUT
1 3 5 7 9 11 13 15
2 4 6 8 10 12 KEY No pin 16
NC COP_TRST COP_VDD_SENSE COP_CHKSTP_IN NC NC
GND
Figure 79. COP Connector Physical Pinout
3.11
3.11.1
Guidelines for High-Speed Interface Termination
SerDes1 Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However, the SerDes must always have power applied to its supply pins. There are several reserved pins that need to be either left floating or connected to XGND. See SerDes1 in Table 1Table 1 for details. The following pins must be left unconnected (float): * SD1_TX[7:4] * SD1_TX[7:4] * Reserved pins T22, T23 The following pins must be connected to XGND: * SD1_RX[7:4] * SD1_RX[7:4] * SD1_REF_CLK * SD1_REF_CLK The POR configuration pin cfg_io_ports[0:2] on TSEC3_TXD[6:3] can be used to power down SerDes 1 block for power saving. Note that both SVDD and XVDD must remain powered.
3.11.2
SerDes 1 Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected (float) if not used: * SD1_TX[7:4] * SD1_TX[7:4] * Reserved pins: T22, T23
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 119
Guidelines for High-Speed Interface Termination
The following pins must be connected to XGND if not used: * * * * SD1_RX[7:4] SD1_RX[7:4] SD1_REF_CLK SD1_REF_CLK
3.11.3
SerDes 2 Interface Entirely Unused
If the high-speed SerDes 2 interface (SGMII/ SATA) is not used at all, the unused pin should be terminated as described in this section. There are several Reserved pins that need to be either left floating or connected to X2GND. See SerDes2 in Table 1Table 1 for details. The following pins must be left unconnected (float): * * * * * * * SD2_TX[0] SD2_TX[0] Reserved pins L8, L9 SD2_RX[0] SD2_RX[0] SD2_REF_CLK SD2_REF_CLK
The following pins must be connected to X2GND:
The POR configuration pin cfg_srds2_prtcl[0:2] on TSEC1_TXD[2], TSEC3_TXD[2], TSEC_1588_PUSLE_OUT1 can be used to power down SerDes 2 block for power saving. Note that both S2VDD and X2VDD must remain powered.
4
Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 4.1, "Part Numbers Fully Addressed by This Document."
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 120 Freescale Semiconductor
Part Numbers Fully Addressed by This Document
4.1
MPC
Part Numbers Fully Addressed by This Document
Table 82. Device Nomenclature
nnnn E Security Engine C Tiers and Temperature Range VT Package 1 VT = FC-PBGA (lead free) PX = plastic Standard AA Processor Frequency 2 AK = 600 MHz AN = 800 MHz AQ = 1000 MHz AT = 1250 MHz AU = 1333 MHz AV = 1500 MHz X DDR Frequency3 G = 400 MHz H = 500 MHz J = 533 MHz L = 667 MHz R Revision Level --
Product Part Code Identifier MPC 8536 8535
A = Commercial Tier standard temperature E = included range(0 to 90C) B or Blank =Industrial Tier standard temperature range(0 to 105C) C = Industrial Tier Blank = not Extended temperature included range(-40 to 105C)
--
Notes: 1. See Section 5, "Package Information," for more information on available package types. 2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies. 3. See Table 84 for the corresponding maximum platform frequency
4.2
Part Marking
Parts are marked as in the example shown in Figure 80.
MPC853nVTnnnn ATWLYYWW MMMMM CCCCC YWWLAZ
Notes:
FC-PBGA
MMMMM is the 5-digit mask number. ATWLYYWW is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 80. Part Marking for FC-PBGA Device
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 121
Part Numbering
4.3
Part Numbering
Table 83. MPC8535 Part Numbers Commercial Tier
Core/Platform/ DDR (MHz) 600/400/400 800/400/400 1000/400/400 1250/500/500 Standard Temp Without Security MPC8535AVTAKG MPC8535AVTANG MPC8535AVTAQG MPC8535AVTATH Standard Temp With Security MPC8535EAVTAKG MPC8535EAVTANG MPC8535EAVTAQG MPC8535EAVTATH Notes -- -- -- --
Table 83 and Table 84 list all part numbers that are offered for MPC8535E.
Table 84. MPC8535 Part Numbers Industrial Tier
Core/Platform/ DDR (MHz) 600/400/400 800/400/400 1000/400/400 1250/500/500 Standard Temp Without Security MPC8535BVTAKG MPC8535BVTANG MPC8535BVTAQG MPC8535BVTATH Standard Temp With Security MPC8535EBVTAKG MPC8535EBVTANG MPC8535EBVTAQG MPC8535EBVTATH Extended Temp Without Security MPC8535CVTAKG MPC8535CVTANG MPC8535CVTAQG MPC8535CVTATH Extended Temp With Security MPC8535ECVTAKG MPC8535ECVTANG MPC8535ECVTAQG MPC8535ECVTATH Notes --
5
5.1
Package Information
Package Parameters for the MPC8535E FC-PBGA
Package outline Interconnects Pitch Minimum module height Maximum module height Solder Balls Ball diameter (typical) 29 mm x 29 mm 783 1 mm 2.23 mm 2.8 mm 96.5Sn/3.5Ag 0.6 mm
This section details package parameters, pin assignments, and dimensions.
The package parameters are as provided in the following list. The package type is 29 mm x 29 mm, 783 flip chip plastic ball grid array (FC-PBGA) without a lid.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 122 Freescale Semiconductor
Mechanical Dimensions of the MPC8535E FC-PBGA
5.2
Mechanical Dimensions of the MPC8535E FC-PBGA
The mechanical dimensions and bottom surface nomenclature of the MPC8535E, 783 FC-PBGA package are shown in Figure 81.
Figure 81. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8535E FC-PBGA NOTES for Figure 81
1. 2. 3. 4. 5. 6. 7. All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. Maximum solder ball diameter measured parallel to datum A Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Capacitors may not be present on all devices Caution must be taken not to short exposed metal capacitor pads on package top. All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 123
Mechanical Dimensions of the MPC8535E FC-PBGA
6
* *
Product Documentation
MPC8536E Integrated Processor Reference Manual (document number: MPC8536ERM) e500 PowerPC Core Reference Manual (document number: E500CORERM)
The following documents are required for a complete description of the device and are needed to design properly with the part.
7
Document Revision History
Table 85. Document Revision History
Table 85 provides a revision history for the MPC8535E hardware specification.
Revision 2
Date 09/2009
Substantive Change(s) * In Section 1, "Pin Assignments and Reset States,"updated the first sentence of the note to say, "The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration." * In Table 40, "SGMII DC Receiver Electrical Characteristics," changed LSTSAB to LSTSA and LSTSEF to LSTSE for Note 4. * In Table 80, "MPC8535E Thermal Model," updated die value and bump/underfill value. * Updated Figure 81, "Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8535E FC-PBGA," and its notes. * In Table 3, "Recommended Operating Conditions," for VDD_CORE, removed 1.1 55 mV. * In Table 5, "MPC8535E Power Dissipation 5," remove note 5. * In Table 5, "MPC8535E Power Dissipation 5," changed an "--"' to "0." * Initial public release.
1
09/2009
0
08/2009
MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 124 Freescale Semiconductor
Mechanical Dimensions of the MPC8535E FC-PBGA
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MPC8535E PowerQUICCTM III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 125
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.
Freescale and the Freescale logo are trademarks or registered trademarks of Freescale Semiconductor, Inc. in the U.S. and other countries. All other product or service names are the property of their respective owners. IEEE 802.16, 802.3,1588, and 1149.1 are registered trademarks of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. (c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Document Number: MPC8535EEC Rev. 2 09/2009

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